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參數(shù)資料
| 型號： | ZL50023GAC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Enhanced 4 K Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA256 |
| 封裝： | 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256 |
| 文件頁數(shù)： | 29/80頁 |
| 文件大小： | 1341K |
| 代理商： | ZL50023GAC |
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ZL50023
Data Sheet
29
Zarlink Semiconductor Inc.
11.0 Connection Memory Block Programming
This feature allows for fast initialization of the connection memory after power up.
11.1 Memory Block Programming Procedure
1. Set MBPE (bit 3) in the Control Register (CR) from low to high.
2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded
into CM_L.
3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The val-
ues stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15
- 3) and the programmable values in the CM_H (bits 4 - 0) will be loaded with zero values.
The following tables show the resulting values that are in the CM_L and CM_H connection memory locations.
Note: Bits 15 to 5 are reserved in Connection Memory High and should always be 0.
It takes at least two frame periods (250
μ
s) to complete a block program cycle.
MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming
process has completed.
MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block
programming process. This is not an automatic action taken by the device and must be performed manually.
Note
: Once the block program has been initiated, it can be terminated at any time prior to completion by setting
MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low. If the
MBPE bit was used to terminate the block programming, the MBPS bit will have to be set low before enabling other
device operations.
12.0 Device Performance Divided Clock and Multiplied Clock Modes
This device has two main operating modes - Divided Clock mode and Multiplied Clock mode.
In Multiplied Clock mode, output clocks and frame pulses are generated based on CKi and FPi. In Divided Clock
mode, output clocks and frame pulses are directly divided from CKi/FPi; therefore, the output clock rate cannot
exceed the CKi rate. In Multiplied Clock mode, the output clocks and frame pulses are generated from a clock
internal to the device and are synchronized to CKi and FPi. All specified frequencies are available on CKo[0:3] in
Multiplied Clock mode.
Table 8, “ZL50023 Operating Modes” on page 30 summarizes the different modes of operation available within the
ZL50023. Each Major mode (explained below) has an associated Minor mode that is determined by setting the
MODE_4M Input Control pins and the OPM bit in the Control Register (Table 14, “Control Register (CR) Bits” on
page 36) indicated in the table.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
BPD2
BPD1
BPD0
Table 6 - Connection Memory Low After Block Programming
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 7 - Connection Memory High After Block Programming
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