參數(shù)資料
型號(hào)： ZL50212GB
元件分類(lèi)： 參考電壓二極管
英文描述： Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode
中文描述： 250 的低電流運(yùn)算，低反向泄露，低噪聲穩(wěn)壓二極管
文件頁(yè)數(shù)： 36/40頁(yè)
文件大?。?/td> 549K
代理商： ZL50212GB
ZL50212
Data Sheet
36
SEMICMF.019
Main Control Register 1 (EC Group 1)
Main Control Register 2 (EC Group 2)
Main Control Register 3 (EC Group 3)
Main Control Register 4 (EC Group 4)
Main Control Register 5 (EC Group 5)
Main Control Register 6 (EC Group 6)
Main Control Register 7 (EC Group 7)
Main Control Register 8 (EC Group 8)
Main Control Register 9 (EC Group 9)
Main Control Register 10 (EC Group 10)
Main Control Register 11 (EC Group 11)
Main Control Register 12 (EC Group 12)
Main Control Register 13 (EC Group 13)
Main Control Register 14 (EC Group 14)
Main Control Register 15 (EC Group 15)
Power-up 00
hex
Bit 6
Bit 5
Unused
Unused
Functional Description of Register Bits
Unused Bits.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711)
PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM
code
.
A/
μ
Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, select
μ
-Law companded
PCM code
.
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo cancellers A and B execute their initialization routine which presets their registers, Base
Address+00
hex
to Base Address+3F
hex
, to the default Reset Value and clears the Adaptive Filter
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their specific
application.
R/W Address: 401hex
R/W Address: 402hex
R/W Address: 403hex
R/W Address: 404hex
R/W Address: 405hex
R/W Address: 406hex
R/W Address: 407hex
R/W Address: 408hex
R/W Address: 409hex
R/W Address: 40Ahex
R/W Address: 40Bhex
R/W Address: 40Chex
R/W Address: 40Dhex
R/W Address: 40Ehex
R/W Address: 40Fhex
Bit 7
Unused
Bit 4
MTDBI
Bit 3
MTDAI
Bit 2
Format
Bit 1
Law
Bit 0
PWUP
Unused
MTDBI
MTDAI
Format
Law
PWUP
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