
329
APPENDIX C INDEX
[G]
general registers.....................................................47
global pointer ..........................................................47
[H]
halfword access ......................................................78
HALT mode...........................................................133
handling of unused pins .........................................43
HLDAK ....................................................................40
HLDRQ....................................................................40
[I]
IC .............................................................................42
I/O circuits of pins...................................................44
I/O circuit type of each pin .....................................43
ID .................................................................... 49, 115
IDLE ......................................................................132
IDLE mode ............................................................135
idle state insertion function ....................................83
ILGOP .....................................................................96
illegal op code definition ......................................119
IMS1n0 to IMS1n3 (n = 1 to 4)............................150
in-service priority register.....................................115
initial value of each register after reset...............299
initialize .................................................................298
instruction set list..................................................319
INTAD......................................................................97
INTC ........................................................................25
INTCM4 ...................................................................97
INTCSI0 to INTCSI3...............................................97
internal block diagram ............................................24
internal peripheral I/O interface .............................93
internal RAM area ..................................................60
internal ROM area ..................................................57
internal units ...........................................................25
interrupt
control register .............................................112
controller ........................................................25
latency time..................................................123
list ...................................................................96
processing function .......................................95
source register ...............................................48
stack pointer ..................................................47
table................................................................58
interval timer .........................................................169
INTM0....................................................................102
INTM1 to INTM4 .......................................... 114, 155
INTOV11 to INTOV14 ............................................96
INTP110 to INTP113 ..............................................35
INTP120 to INTP123 ..............................................36
INTP130 to INTP133 ..............................................37
INTP140 to INTP143 ..............................................41
INTP1mn/INTCC1mn
(m = 1 to 4, n = 0 to 3) ................................... 96, 97
INTSER0, INTSER1 ...................................... 97, 190
INTSR0, INTSR1 ........................................... 97, 190
INTST0, INTST1 ............................................ 97, 190
ISPR ......................................................................115
ISPR0 to ISPR7....................................................115
[L]
LBEN .......................................................................39
link pointer ..............................................................47
[M]
maskable interrupt ................................................103
maskable interrupt status flag..............................115
memory
block function.................................................80
boundary operation condition .......................92
expansion mode register...............................64
map ................................................................54
read ................................................................85
write................................................................89
MM...........................................................................64
MM0 to MM3 ...........................................................64
MOD0 to MOD3 ....................................................197
MODE......................................................................41
MS .........................................................................216
multiple interrupt processing ................................121
[N]
NMI ..........................................................................42
noise elimination circuit ........................................295
noise elimination of NMI pin ................................102
nonlinearity error...................................................241
non-maskable interrupt...........................................98
non-maskable interrupt status flag ......................102
normal operation mode ..........................................50
note (timer/counter function) ................................177
NP............................................................................49
[O]
off-board programming.........................................301
on-board programming .........................................301
operation in power save mode ..............................84