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CHAPTER 3 CPU FUNCTIONS
3.3 Operation Modes
3.3.1 Operation modes
The V853 has the following operation modes.
(1) Normal operation mode
(a) Single-chip mode
After the system has been released from the reset status, the pins related to the bus interface are set
for port mode, execution branches to the reset entry address of the internal ROM, and instruction
processing is started. However, access to external memory and peripheral devices can be enabled by
setting in the external memory expansion mode register by instruction (MM: refer to
3.4.7
).
(b) ROM-less mode (
μ
PD703003 and 70F3003)
After the system has been released from the reset status, the pins related to bus interface are set for control
mode, execution branches to the reset address of external memory, and instruction processing is started.
Instruction fetch and data access to internal ROM are disabled.
(2) Flash memory programming mode (
μ
PD70F3003, 70F3003A, and 70F3025A)
Specifying this mode enables the program operation to internal flash memory by the flash programmer.
3.3.2 Specifying operation mode
(1) Normal operation mode
(a)
μ
PD703003 and 70F3003
The operation mode of the V853 is specified depending on the status of the MODE pin. Set these pins
in the application system.
If the setting is changed during operation, the operation is not guaranteed.
MODE
Operation Mode
0
ROM-less mode
1
Single-chip mode
(b)
μ
PD703003A, 70F3003A, 703025A, and 70F3025A
The operation mode is fixed to single-chip mode irrespective of the MODE pin status.
(2) Flash memory programming mode
The operation mode of the V853 is specified depending on the MODE pin and V
PP
pin. This pin specification
should be fixed in application system and do not change during the operation.
The operation is not guaranteed if the status is changed during the operation.
Pin status
V
PP
0 V
Operation Mode
MODE
1
Normal operation mode
10 V
1
Flash memory programming mode
Refer to
CHAPTER 14 FLASH MEMORY
(
μ
PD70F3003, 70F3003A, AND 70F3025A)
.