
- i -
CONTENTS
CHAPTER 1
GENERAL..........................................................................................................................
1
1.1
FUNCTION OVERVIEW ..........................................................................................
2
1.2
ORDERING INFORMATION....................................................................................
DIFFERENCES AMONG
μ
PD750108 SUBSERIES PRODUCTS ........................
BLOCK DIAGRAM ...................................................................................................
3
1.3
4
1.4
5
1.5
PIN CONFIGURATION (TOP VIEW) ......................................................................
6
CHAPTER 2
PIN FUNCTIONS ...............................................................................................................
9
2.1
PIN FUNCTIONS OF THE
μ
PD750108 ..................................................................
PIN FUNCTIONS .....................................................................................................
9
2.2
13
2.2.1
P00-P03 (PORT0), P10-P13 (PORT1) ......................................................
13
2.2.2
P20-P23 (PORT2), P30-P33 (PORT3), P40-P43 (PORT4),
P50-P53 (PORT5), P60-P63 (PORT6), P70-P73 (PORT7) .....................
13
2.2.3
P80, P81 (PORT8)......................................................................................
14
2.2.4
TI0 ...............................................................................................................
14
2.2.5
PTO0, PTO1 ...............................................................................................
15
2.2.6
PCL..............................................................................................................
15
2.2.7
BUZ .............................................................................................................
15
2.2.8
SCK, SO/SB0, SI/SB1 ................................................................................
15
2.2.9
INT4.............................................................................................................
15
2.2.10 INT0, INT1...................................................................................................
16
2.2.11 INT2.............................................................................................................
16
2.2.12 KR0-KR3, KR4-KR7....................................................................................
17
2.2.13 CL1, CL2 .....................................................................................................
17
2.2.14 XT1, XT2 .....................................................................................................
17
2.2.15 RESET ........................................................................................................
18
2.2.16 V
DD
..............................................................................................................
2.2.17 V
SS
..............................................................................................................
2.2.18 IC (for the
μ
PD750104,
μ
PD750106, and
μ
PD750108 only) ...................
2.2.19 V
PP
(for the
μ
PD75P0116 only) .................................................................
2.2.20 MD0-MD3 (for the
μ
PD75P0116 only) .......................................................
2.2.21 D0-D7 (for the
μ
PD75P0116 only) .............................................................
PIN INPUT/OUTPUT CIRCUITS .............................................................................
18
18
18
18
18
18
2.3
19
2.4
CONNECTION OF UNUSED PINS .........................................................................
21
CHAPTER 3
FEATURES OF THE ARCHITECTURE AND MEMORY MAP.......................................
23
3.1
DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES ..................
23
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