
- ii -
3.1.1
Data Memory Bank Structure .....................................................................
23
3.1.2
Data Memory Addressing Modes...............................................................
25
3.2
GENERAL REGISTER BANK CONFIGURATION..................................................
36
3.3
MEMORY-MAPPED I/O...........................................................................................
41
CHAPTER 4
INTERNAL CPU FUNCTIONS..........................................................................................
47
4.1
Mk I MODE/Mk II MODE SWITCH FUNCTIONS....................................................
47
4.1.1
Differences between Mk I Mode and Mk II Mode.....................................
47
4.1.2
Setting of the Stack Bank Selection Register (SBS)................................
48
4.2
PROGRAM COUNTER (PC) ..................................................................................
49
4.3
PROGRAM MEMORY (ROM) .................................................................................
50
4.4
DATA MEMORY (RAM) ...........................................................................................
55
4.4.1
Data Memory Configuration........................................................................
55
4.4.2
Specification of a Data Memory Bank........................................................
56
4.5
GENERAL REGISTER.............................................................................................
58
4.6
ACCUMULATOR......................................................................................................
59
4.7
STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS)............
60
4.8
PROGRAM STATUS WORD (PSW) .......................................................................
64
4.9
BANK SELECT REGISTER (BS) ............................................................................
67
CHAPTER 5
PERIPHERAL HARDWARE FUNCTIONS.......................................................................
69
5.1
DIGITAL I/O PORTS..............................................................................................
69
5.1.1
Types, Features, and Configurations of Digital I/O Ports ........................
70
5.1.2
I/O Mode Setting.........................................................................................
76
5.1.3
Digital I/O Port Manipulation Instructions ..................................................
78
5.1.4
Digital I/O Port Operation ...........................................................................
81
5.1.5
Specification of Built-In Pull-Up Resistors .................................................
83
5.1.6
I/O Timing of Digital I/O Ports ....................................................................
84
5.2
CLOCK GENERATOR .............................................................................................
86
5.2.1
Clock Generator Configuration...................................................................
86
5.2.2
Functions and Operations of the Clock Generator...................................
87
5.2.3
System Clock and CPU Clock Setting .......................................................
98
5.2.4
Clock Output Circuit.................................................................................... 100
5.3
BASIC INTERVAL TIMER/WATCHDOG TIMER .................................................... 103
5.3.1
Configuration of the Basic Interval Timer/Watchdog Timer ..................... 103
5.3.2
Basic Interval Timer Mode Register (BTM) ............................................... 103
5.3.3
Watchdog Timer Enable Flag (WDTM)...................................................... 105
5.3.4
Operation of the Basic Interval Timer ........................................................ 105
5.3.5
Operation of the Watchdog Timer.............................................................. 106
5.3.6
Other Functions .......................................................................................... 107