
- vi -
LIST OF FIGURES (1/4)
Figure No.
Title
Page
2-1
Pin Input/Output Circuits ...................................................................................................
19
3-1
Use of MBE = 0 Mode and MBE = 1 Mode ......................................................................
24
3-2
Data Memory Organization and Addressing Range of Each Addressing Mode ............
26
3-3
Updating Static RAM Addresses.......................................................................................
30
3-4
Example of Register Bank Selection ................................................................................
37
3-5
General Register Configuration (4-Bit Processing) ..........................................................
39
3-6
General Register Configuration (8-Bit Processing) ..........................................................
μ
PD750108 I/O Map ..........................................................................................................
40
3-7
42
4-1
Stack Bank Selection Register Format .............................................................................
48
4-2
Program Counter Organization .........................................................................................
Program Memory Map (in
μ
PD750104) ............................................................................
Program Memory Map (in
μ
PD750106) ............................................................................
Program Memory Map (in
μ
PD750108) ............................................................................
Program Memory Map (in
μ
PD75P0116)..........................................................................
Data Memory Map .............................................................................................................
49
4-3
51
4-4
52
4-5
53
4-6
54
4-7
56
4-8
General Register Format...................................................................................................
58
4-9
Register Pair Format .........................................................................................................
59
4-10
Accumulator .......................................................................................................................
59
4-11
Format of Stack Pointer and Stack Bank Select Register ...............................................
61
4-12
Data Saved to the Stack Memory (Mk I Mode) ................................................................
62
4-13
Data Restored from the Stack Memory (Mk I Mode) .......................................................
62
4-14
Data Saved to the Stack Memory (Mk II Mode) ...............................................................
63
4-15
Data Restored from the Stack Memory (Mk II Mode) ......................................................
63
4-16
Program Status Word Format ...........................................................................................
64
4-17
Bank Select Register Format ............................................................................................
67
5-1
Data Memory Addresses of Digital Ports..........................................................................
69
5-2
Configurations of Ports 0 and 1 ........................................................................................
71
5-3
Configurations of Ports 2 and 7 ........................................................................................
72
5-4
Configurations of Ports 3n and 6n (n = 0 to 3).................................................................
73
5-5
Configurations of Ports 4 and 5 ........................................................................................
74
5-6
Configuration of Port 8 ......................................................................................................
75
5-7
Formats of Port Mode Registers .......................................................................................
77
5-8
Pull-Up Resistor Specification Register Format ...............................................................
84