
- viii -
LIST OF FIGURES (3/4)
Figure No.
Title
Page
5-45
Operations of RELT and CMDT ........................................................................................ 144
5-46
Transfer Bit Switching Circuit............................................................................................ 144
5-47
Example of Two-Wire Serial I/O System Configuration ................................................... 147
5-48
Timing of Two-Wire Serial I/O Mode................................................................................. 150
5-49
Operations of RELT and CMDT ........................................................................................ 151
5-50
Example of SBI System Configuration.............................................................................. 153
5-51
Timing of SBI Transfer ...................................................................................................... 155
5-52
Bus Release Signal ........................................................................................................... 156
5-53
Command Signal ............................................................................................................... 156
5-54
Address .............................................................................................................................. 156
5-55
Slave Selection Using an Address.................................................................................... 157
5-56
Command........................................................................................................................... 157
5-57
Data.................................................................................................................................... 157
5-58
Acknowledge Signal .......................................................................................................... 158
5-59
Busy and Ready Signals ................................................................................................... 159
5-60
Operations of RELT, CMDT, RELD, and CMDD (Master) ............................................... 164
5-61
Operations of RELT, CMDT, RELD, and CMDD (Slave) ................................................. 164
5-62
Operation of ACKT ............................................................................................................ 165
5-63
Operation of ACKE ............................................................................................................ 165
5-64
Operation of ACKD............................................................................................................ 166
5-65
Operation of BSYE ............................................................................................................ 167
5-66
Pin Configuration ............................................................................................................... 170
5-67
Address Transfer Operation from Master Device to Slave Device (WUP = 1) .............. 172
5-68
Command Transfer Operation from Master Device to Slave Device.............................. 173
5-69
Data Transfer Operation from Master Device to Slave Device....................................... 174
5-70
Data Transfer Operation from Slave Device to Master Device....................................... 175
5-71
Example of Serial Bus Configuration ................................................................................ 177
5-72
Transfer Format of the READ Command ......................................................................... 178
5-73
Transfer Format of the WRITE and END Commands...................................................... 179
5-74
Transfer Format of the STOP Command.......................................................................... 179
5-75
Transfer Format of the STATUS Command ..................................................................... 180
5-76
Status Format of the STATUS Command ........................................................................ 180
5-77
Transfer Format of the RESET Command ....................................................................... 181
5-78
Transfer Format of the CHGMST Command.................................................................... 181
5-79
Master and Slave Operation in Case of Error .................................................................. 182
5-80
SCK/P01 Pin Circuit Configuration ................................................................................... 183
5-81
Format of the Bit Sequential Buffer .................................................................................. 184