CHAPTER 5 CLOCK GENERATOR
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5.6 Changing System Clock and CPU Clock Settings
5.6.1 Time required for switchover between system clock and CPU clock
The system clock and CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS)
of the processor clock control register (PCC).
The actual switchover operation is not performed directly after writing to the PCC, but operation continues on
the pre-switchover clock for several instructions (see
Table 5-3.
).
Determination as to whether the system is operating on the main system clock or the subsystem clock is
performed by bit 5 (CLS) of the PCC register.
Table 5-3. Maximum Time Required for CPU Clock Switchover
CSS
PCC2 PCC1 PCC0
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
CSS PCC2 PCC1 PCC0
CSS PCC2 PCC1 PCC0
CSS PCC2 PCC1 PCC0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
x
x
x
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
×
×
×
1
0
Set Values after Switchover
16 instructions
f /2f
instructions
(64 instructions)
f /4f
instructions
(32 instructions)
f /8f
instructions
(16 instructions)
4 instructions
2 instructions
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
2 instructions
2 instructions
2 instructions
4 instructions
4 instructions
4 instructions
16 instructions
16 instructions
16 instructions
8 instructions
8 instructions
8 instructions
8 instructions
X
XT
X
XT
X
XT
f /16f
instructions
(8 instructions)
f /32f
instructions
(4 instructions)
X
XT
X
XT
Set Values before Switchover
Caution
Selection of the CPU clock cycle scaling factor (PCC0 to PCC2) and switchover from the main
system clock to the subsystem clock (changing CSS from 0 to 1) should not be performed
simultaneously.
Simultaneous setting is possible, however, for selection of the CPU clock cycle scaling factor
(PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing
CSS from 1 to 0).
Remarks 1.
One instruction is the minimum instruction execution time with the pre-switchover CPU clock.
2.
Figures in parentheses apply to operation with f
X
= 5.0 MHz or f
XT
= 32.768 kHz.