CHAPTER 16 FIP CONTROLLER/DRIVER
277
CHAPTER 16 FIP CONTROLLER/DRIVER
16.1 FIP Controller/Driver Functions
The functions of the FIP controller/driver incorporated in the
μ
PD78044F Subseries are as follows.
(1) Automatically outputs the segment signals (DMA operation) and digit signals by automatically reading
data displayed.
(2) Controls 9- to 24-segment and 2- to 16-digit FIPs (fluorescent indicator panel) using display mode
registers 0 and 1 (DSPM0 and DSPM1).
(3) Pins not used for FIP display can be used as output and input/output ports.
(4) Luminance can be adjusted in 8 levels using display mode register 1 (DSPM1).
(5) Incorporates hardware for key scan application.
Generates interruption signals (INTKS) indicating key scan timing.
Outputs key scan signals from segment output pins by setting key scan data to port 11 and port 12.
Detects timings at which key scan data are output by the key scan flag (KSF).
(6) Incorporates a high voltage-resistant output buffer that can directly drive the FIP.
(7) The display output pin can be connected to a pull-down resistor by mask option.
Cautions
1.
The FIP controller/driver can be operated only when f
x
or f
x
/2 is selected for the CPU clock.
When performing FIP display, set bit 4 (CSS) of the processor control register (PCC) to
0 and bits 2 to 0 (PCC2 to PCC0) of the PCC register to 000 or 001. Data will not be displayed
properly if clocks other than these are used (including the subsystem clock). To stop the
main oscillation, be sure to specify "display stop" by setting bits 7 to 4 (DIGS3 to DIGS0)
of the display mode register 1 (DSPM1) to 0000.
When using the FIP controller/driver, set the pins of ports 11 and 12 used as segment
outputs to the output mode (set 0 to the bits corresponding to port mode registers 11 and
12).
2.