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ix
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LIST OF FIGURES (1/8)
Figure No.
Title
Page
3-1
Pin Input/Output Circuit of List .......................................................................................
38
4-1
Pin Input/Output Circuit of List .......................................................................................
54
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
Memory Map (
m
PD78062, 78062Y).................................................................................
Memory Map (
m
PD78063, 78063Y).................................................................................
Memory Map (
m
PD78064, 78064Y).................................................................................
Memory Map (
m
PD78P064, 78P064Y) ............................................................................
Data Memory Addressing (
m
PD78062, 78062Y)..............................................................
Data Memory Addressing (
m
PD78063, 78063Y)..............................................................
Data Memory Addressing (
m
PD78064, 78064Y)..............................................................
Data Memory Addressing (
m
PD78P064, 78P064Y) .........................................................
Program Counter Configuration.......................................................................................
Program Status Word Configuration ...............................................................................
Stack Pointer Configuration ............................................................................................
Data to be Saved to Stack Memory ................................................................................
Data to be Reset from Stack Memory ............................................................................
General Register Configuration .......................................................................................
57
58
59
60
63
64
65
66
67
67
68
68
69
70
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
Port Types ......................................................................................................................
P00 and P07 Configurations............................................................................................
P01 to P05 Configurations ..............................................................................................
P10 to P17 Configurations ..............................................................................................
P25, P26 Configurations (
m
PD78064 subseries)..............................................................
P27 Configuration (
m
PD78064 subseries)........................................................................
P25, P26 Configurations (
m
PD78064Y subseries)............................................................
P27 Configuration (
m
PD78064Y subseries)......................................................................
P30 to P37 Configurations ..............................................................................................
P70 Configuration ...........................................................................................................
P71 and P72 Configurations............................................................................................
P80 to P87 Configurations ..............................................................................................
P90 to P97 Configurations ..............................................................................................
P100 to P103 Configurations ..........................................................................................
P110 to P117 Configurations ..........................................................................................
Block Diagram of Falling Edge Detection Circuit.............................................................
Port Mode Register Format ............................................................................................
Pull-Up Resistor Option Register Format ........................................................................
Key Return Mode Register Format .................................................................................
89
93
93
94
95
96
97
98
99
100
101
102
103
104
105
105
108
109
110