參數(shù)資料
型號(hào)： 0W344-004-XTP
廠商： ON Semiconductor
文件頁(yè)數(shù)： 19/43頁(yè)
文件大小： 0K
描述： DSP BELASIGNA 200 AUDIO 52-NQFN
產(chǎn)品變化通告： BelaSigna 200 QFN Obsolescence 09/Dec/2009
標(biāo)準(zhǔn)包裝： 500
系列： BelaSigna® 200
類型： 音頻處理器
應(yīng)用： 便攜式設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 52-TFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 52-NQFP（8x8）
包裝： 帶卷 (TR)
BelaSigna 200
9.0 External Interfaces
9.1 External Digital Interfaces
9.1.1. Pulse-Code Modulation Interface (PCM I/F)
The PCM interface is a bi-directional, four-wire synchronous serial interface suitable for high-speed digital audio transfer. This
externally-clocked interface is capable of sending data serially at rates up to the clock speed of the RCore, providing the necessary
bandwidth for digital audio. This interface can also be used for a number of other functions, including multi-processing BelaSigna 200
chips. The interface is configurable for glueless connections to four-wire PCM interfaces as well as other BelaSigna 200 chips in a
BelaSigna 200 multi-chip configuration. Both master and slave modes are supported. The interface is configured via a memory-mapped
configuration register and interacts with the RCore through memory-mapped control registers and interrupts. Refer to Section 12.1 for
timing specifications.
9.1.2. General-Purpose Input/Output (GPIO)
Up to 16 GPIO pins are available to be configured as inputs or as outputs. All GPIO pins are pulled up internally. Data are read or
written via a memory-mapped control register. GPIO pins can be used to interface to digital switches, other devices, etc. The direction
of each bit is programmable via a direction register. Refer to Section 12.2 for timing specifications.
9.1.3. Serial Peripheral Interface (SPI) Port
The SPI port allows BelaSigna 200 to communicate synchronously with other devices such as external memory or EEPROM. This SPI
interface conforms to the standard SPI bus protocol supporting modes zero and two as a master, and transfer speeds up to half the
system clock frequency. The interface is configured via a memory-mapped configuration register and interacts with the RCore through
memory-mapped control registers and interrupts. Refer to Section 12.3 for timing specifications.
9.1.4. RS-232 Universal Asynchronous Receiver/Transmitter (UART)
The general-purpose UART is a low-voltage RS-232-compatible interface. All data are transmitted and received with eight data bits, no
parity and one stop bit (8N1). A range of standard data rates, up to a maximum of 115.2kbps, is supported. The interface is configured
via a memory-mapped configuration register and interacts with the RCore through memory-mapped control registers and interrupts.
9.1.5. Debug Port
The debug port is also a low-voltage RS-232-based UART, and it interfaces directly to the program controller. This interface differs from
the general-purpose UART in its access path to the RCore. It is used primarily by the evaluation and development tools to interface to,
program and debug BelaSigna 200 applications. Data rates up to 115.2kbps are supported. The protocol uses eight data bits, no parity
and one stop bit (8N1).
9.1.6. Two-Wire Synchronous Serial (TWSS) Interface
This industry standard two-wire high-speed synchronous serial interface allows communication to a variety of other integrated circuits
and memories. On BelaSigna 200, this interface operates in slave mode only. Data rates up to 400kbps are supported for MCLK
frequencies higher than 1.28MHz; for lower MCLK frequencies, the maximum rate is 100kbps. The interface is configured via memory
mapped configuration registers and interacts with the RCore through memory-mapped control registers and interrupts. The TWSS
interface is compatible with the Philips' I
2C protocol.
9.1.7. I
2S Interface
This industry standard digital audio interface uses a three-wire serial protocol to transmit and receive audio between BelaSigna 200 and
other systems. The interface operates at the system clock frequency and BelaSigna 200 always assumes master functionality.
Rev. 16 | Page 26 of 43 | www.onsemi.com
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