參數資料
| 型號： | 100-1221-3 |
| 廠商： | Bluetechnix |
| 文件頁數： | 19/68頁 |
| 文件大小： | 0K |
| 描述： | CORE MOD CM-BF537E 600MHZ CONN |
| 標準包裝： | 1 |
| 模塊/板類型： | 核心模塊 |
| 其它名稱： | 100-1221 100-1221-ND |
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Rev. J
|
Page 26 of 68
|
February 2014
CIN
Input
Capacitance
13, 14
fIN = 1 MHz,
TAMBIENT = 25°C,
VIN = 2.5 V
88
pF
IDD-IDLE
VDDINT Current in
Idle
VDDINT = 1.0 V,
fCCLK = 50 MHz,
TJ = 25°C, ASF = 0.43
14
24
mA
IDD-TYP
VDDINT Current
VDDINT = 1.14 V,
fCCLK =300 MHz,
TJ = 25°C, ASF = 1.00
100
113
mA
IDD-TYP
VDDINT Current
VDDINT = 1.14 V,
fCCLK =400 MHz,
TJ = 25°C, ASF = 1.00
125
138
mA
IDDDEEPSLEEP
15
VDDINT Current in
Deep Sleep
Mode
VDDINT = 1.0 V,
fCCLK = 0 MHz,
TJ = 25°C, ASF = 0.00
616
mA
IDDSLEEP
VDDINT Current in
Sleep Mode
VDDINT = 1.0 V,
fSCLK = 25 MHz,
TJ = 25°C
9.5
19.5
mA
IDD-TYP
VDDINT Current
VDDINT = 1.20 V,
fCCLK =533 MHz,
TJ = 25°C, ASF = 1.00
185
mA
IDD-TYP
VDDINT Current
VDDINT = 1.30 V,
fCCLK =600 MHz,
TJ = 25°C, ASF = 1.00
227
mA
IDDHIBERNATE
15, 16 V
DDEXT Current in
Hibernate State
VDDEXT = 3.60 V,
CLKIN=0 MHz,
TJ =maximum, with
voltage regulator off
(VDDINT =0 V)
50
100
50
100
A
IDDRTC
VDDRTC Current
VDDRTC = 3.3 V, TJ= 25°C
20
A
IDDDEEPSLEEP
VDDINT Current in
Deep Sleep
Mode
fCCLK = 0 MHz,
fSCLK =0 MHz
mA
IDDSLEEP
15, 17
VDDINT Current in
Sleep Mode
fCCLK = 0 MHz,
fSCLK 0 MHz
IDDDEEPSLEEP + (0.14
× VDDINT × fSCLK)
IDDDEEPSLEEP + (0.14
× VDDINT × fSCLK)
mA
IDDINT
18
VDDINT Current
fCCLK 0 MHz,
fSCLK 0 MHz
IDDSLEEP +
(Table 18 × ASF)
IDDSLEEP +
(Table 18 × ASF)
mA
1 Applies to all 300 MHz and 400 MHz speed grade models. See Ordering Guide on Page 67.
2 Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 67.
3 Applies to all output and bidirectional pins except port F pins, port G pins, and port H pins.
4 Applies to port F pins PF7–0.
5 Applies to port F pins PF15–8, all port G pins, and all port H pins.
6 Maximum combined current for Port F7–0.
7 Maximum total current for all port F, port G, and port H pins.
8 Applies to all input pins except PJ4.
9 Applies to input pin PJ4 only.
10Applies to JTAG input pins (TCK, TDI, TMS, TRST).
11Applies to three-statable pins.
12Applies to bidirectional pins PJ2 and PJ3.
13Applies to all signal pins.
14Guaranteed, but not tested.
15See the ADSP-BF537 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
16CLKIN must be tied to VDDEXT or GND during hibernate.
17In the equations, the f
SCLK parameter is the system clock in MHz.
300 MHz/400 MHz
1
500 MHz/533 MHz/600 MHz
2
Parameter
Test Conditions
Min
Typ
Max
Min
Typ
Max
Unit
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