參數(shù)資料
型號(hào)： 100-1221-3
廠商： Bluetechnix
文件頁(yè)數(shù)： 6/68頁(yè)
文件大小： 0K
描述： CORE MOD CM-BF537E 600MHZ CONN
標(biāo)準(zhǔn)包裝： 1
模塊/板類型： 核心模塊
其它名稱： 100-1221
100-1221-ND
Rev. J
|
Page 14 of 68
|
February 2014
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all of
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (VDDINT) to 0 V to provide the greatest power savings. To
preserve the processor state, prior to removing power, any criti-
cal information stored internally (memory contents, register
contents, etc.) must be written to a nonvolatile storage device.
Since VDDEXT is still supplied in this state, all of the external pins
three-state, unless otherwise specified. This allows other devices
that are connected to the processor to still have power applied
without drawing unwanted current.
The Ethernet or CAN modules can wake up the internal supply
regulator. If the PH6 pin does not connect as the PHYINT sig-
nal to an external PHY device, it can be pulled low by any other
device to wake the processor up. The regulator can also be
woken up by a real-time clock wake-up event or by asserting the
RESET pin. All hibernate wake-up events initiate the hardware
reset sequence. Individual sources are enabled by the VR_CTL
register.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in the hiber-
nate state. State variables can be held in external SRAM or
SDRAM. The SCKELOW bit in the VR_CTL register provides a
means of waking from hibernate state without disrupting a self-
refreshing SDRAM, provided that there is also an external pull-
down on the SCKE pin.
Power Savings
As shown in Table 5, the processors support three different
power domains which maximizes flexibility, while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.
The dynamic power management feature allows both the pro-
cessor’s input voltage (VDDINT) and clock frequency (fCCLK) to be
dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in power dissipation, while reducing the voltage by
25% reduces power dissipation by more than 40%. Further,
these power savings are additive, in that if the clock frequency
and supply voltage are both reduced, the power savings can be
dramatic, as shown in the following equations.
The power savings factor (PSF) is calculated as:
where:
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
tNOM is the duration running at fCCLKNOM
tRED is the duration running at fCCLKRED
The percent power savings is calculated as
VOLTAGE REGULATION
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
vide an on-chip voltage regulator that can generate appropriate
VDDINT voltage levels from the VDDEXT supply. See Operating
Conditions on Page 23 for regulator tolerances and acceptable
VDDEXT ranges for specific models.
Figure 5 shows the typical external components required to
complete the power management system. The regulator con-
trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while keeping I/O power supplied. While in
Table 5. Power Domains
Power Domain
VDD Range
All internal logic, except RTC
VDDINT
RTC internal logic and crystal I/O
VDDRTC
All other I/O
VDDEXT
Figure 5. Voltage Regulator Circuit
PSF
fCCLKRED
fCCLKNOM
---------------------
VDDINTRED
VDDINTNOM
--------------------------
2
tRED
tNOM
-----------
=
% power savings
1
PSF
–
100%
=
VDDEXT
(LOW-INDUCTANCE)
VDDINT
VROUT
100μF
VROUT
GND
SHORT AND LOW-
INDUCTANCE WIRE
VDDEXT
+
100μF
10μF
LOW ESR
100nF
SET OF DECOUPLING
CAPACITORS
FDS9431A
ZHCS1000
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
10μH
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