參數(shù)資料
型號(hào): 100-1221-3
廠商: Bluetechnix
文件頁(yè)數(shù): 28/68頁(yè)
文件大小: 0K
描述: CORE MOD CM-BF537E 600MHZ CONN
標(biāo)準(zhǔn)包裝: 1
模塊/板類型: 核心模塊
其它名稱: 100-1221
100-1221-ND
Rev. J
|
Page 34 of 68
|
February 2014
SDRAM Interface Timing
Table 27. SDRAM Interface Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSDAT
DATA15–0 Setup Before CLKOUT
1.5
ns
tHSDAT
DATA15–0 Hold After CLKOUT
0.8
ns
Switching Characteristics
tDCAD
COMMAND
1, ADDR19–1, DATA15–0 Delay After CLKOUT
1 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
4.0
ns
tHCAD
COMMAND
1, ADDR19–1, DATA15–0 Hold After CLKOUT
1.0
ns
tDSDAT
DATA15–0 Disable After CLKOUT
6.0
ns
tENSDAT
DATA15–0 Enable After CLKOUT
0.5
ns
tSCLK
2
2 These limits are specific to the SDRAM interface only. In addition, CLKOUT must always comply with the limits in Table 14 on Page 24.
CLKOUT Period when TJ +105
°C7.5
ns
tSCLK
CLKOUT Period when TJ +105
°C10
ns
tSCLKH
CLKOUT Width High
2.5
ns
tSCLKL
CLKOUT Width Low
2.5
ns
Figure 14. SDRAM Interface Timing
tSCLK
CLKOUT
tSCLKL
tSCLKH
tSSDAT
tHSDAT
tENSDAT
tDCAD
tDSDAT
tHCAD
tDCAD
tHCAD
DATA (IN)
DATA (OUT)
COMMAND,
ADDRESS
(OUT)
NOTE: COMMAND =
SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
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