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參數(shù)資料
| 型號(hào)： | 1048C |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Shielded Paired Cable; Number of Conductors:10; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Number of Pairs:5; Leaded Process Compatible:Yes; Drop Ship:Yes RoHS Compliant: Yes |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大小： | 185K |
| 代理商： | 1048C |
Specifications
ispLSI 1048C/883
10
GND
B2,
M8,
C7,
N7
B8, B13,
N2,
G2,
C8,
H3, H12,
N8
G3, G12, G13,
VCC
M7,
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
J2,
L2,
M3,
P4,
N9,
N11, M10, P13, N12, M11, P14,
M12, N14, M13, L12, M14, L13,
L14, K12, K13, K14,
F13, F12, E14, D14, E13, C14,
D13, E12, B14, C13, D12, A14,
C12, A13, B12, C11, A12, B11,
A11, C10, B10, A10,
B6,
C6,
A5,
B4,
C5,
A2,
C3,
B1,
C2,
D1,
E3,
E2,
J3,
K3,
P2,
M5,
M9, P10, P11, N10, P12,
K1,
N1,
N3,
N5, P5,
L1,
M2,
M4,
K2,
L3,
P3,
M6,
M1,
P1,
N4,
N6,
J12,
J13,
C9,
B5,
C4,
C1,
F3,
B9,
A3,
A1,
D2,
F2
A4,
B3,
D3,
E1,
RESET
H1
Y0
G1
Y1
G14
Y2
H13
Y3
H14
IN 2, IN 4
IN 6 - IN 11
P7,
F14,
P9
A9,
A8,
A7,
A6,
F1
GOE0, GOE1
N13,
B7,
Input
–
Dedicated in-system programming enable input pin. This
pin is brought low to enable the programming mode. The MODE,
SDI, SDO and SCLK options become active.
Input
–
This pin performs two functions. It is a dedicated input pin
when
ispEN
is logic high. When
ispEN
is logic low, it functions as
an input pin to load programming data into the device. SDI/IN 0
also is used as one of the two control pins for the isp state machine.
Input
–
This pin performs two functions. It is a dedicated input pin
when
ispEN
is logic high. When
ispEN
is logic low, it functions as
a pin to control the operation of the isp state machine.
Input/Output
–
This pin performs two functions. It is a dedicated
input pin when
ispEN
is logic high. When
ispEN
is logic low, it
functions as an output pin to read serial shift register data.
Input
–
This pin performs two functions. It is a dedicated input
when
ispEN
is logic high. When
ispEN
is logic low, it functions as
a clock pin for the Serial Shift Register.
Input/Output Pins - These are the general purpose I/O pins used
by the logic array.
Ground (GND)
V
CC
Active Low (0) Reset pin which resets all of the GLB and I/O
registers in the device.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on
the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/
or any I/O cell on the device.
Dedicated clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on
the device.
Dedicated input pins to the device.
Global output enables for all I/Os.
Table 2- 0002C-48C/CPGA
DESCRIPTION
NAME
CPGA PIN NUMBERS
ispEN
H2
SDI/IN 0
1
J1
MODE/IN 1
1
P6
SDO/IN 3
1
P8
SCLK/IN 5
1
J14
1. Pins have dual function capability.
Pin Description
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