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參數(shù)資料
| 型號： | 1048C |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Shielded Paired Cable; Number of Conductors:10; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Number of Pairs:5; Leaded Process Compatible:Yes; Drop Ship:Yes RoHS Compliant: Yes |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 185K |
| 代理商： | 1048C |
Specifications
ispLSI 1048C/883
5
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
t
su3
t
h3
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
Clock Frequency, Max Toggle
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg.
Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
20
21
22
23
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
–
–
DESCRIPTION
1
PARAMETER
#
2
-50
MAX.
22.0
26.0
–
–
–
–
14.0
–
–
16.0
–
20.5
–
27.5
27.5
20.5
20.5
–
–
–
–
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
UNITS
Table 2- 0030-48C/50 mil
–
–
50.3
34.5
58.8
13.0
–
0
15.0
–
0
–
13.5
–
–
–
–
8.5
8.5
3.0
9.0
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
( )
1
( )
1
TEST
4
COND.
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