參數(shù)資料
型號： 20-101-0383
廠商： Rabbit Semiconductor
文件頁數(shù)： 47/80頁
文件大小： 0K
描述： MODULE RABBITCORE RCM2020
標(biāo)準(zhǔn)包裝： 1
系列： RabbitCore®
模塊/板類型： MPU 核心模塊
適用于相關(guān)產(chǎn)品： RCM2020
產(chǎn)品目錄頁面： 620 (CN2011-ZH PDF)
其它名稱： 316-1082
User’s Manual
47
The values from the table above are derived using 55 ns (25.8 MHz version) and 90 ns
(18.4 MHz version) memory access times. External capacitive loading can be improved
by 10 pF for commercial temperature ranges, but do not exceed 100 pF. See the AC timing
specifications in the Rabbit 2000 Microprocessor User’s Manual for more information.
Figure A-4 shows a typical timing diagram for the Rabbit 2000 microprocessor memory
read and write cycles.
Figure A-4. Memory Read and Write Cycles
Tadr is the time required for the address output to reach 0.8 V. This time depends on the
bus loading. A0 has a stronger driver and can handle larger capacitive loads than the other
address lines. Tsetup is the data setup time relative to the clock. Tsetup is specified from
30%/70% of the VDD voltage level. Add 1.5 ns to Tadr for each 10 pF of additional bus
loading above 70 pF.
Tadr
Memory Read (no wait states)
Thold
valid
CLK
A[19:0]
D[7:0]
valid
Tsetup
Thold
Memory Write (no extra wait states)
CLK
A[19:0]
D[7:0]
/CSx
/OEx
/CSx
/WEx
valid
T1
T2
T1
Tw
T2
valid
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