參數(shù)資料
型號： 2097152
廠商： Texas Instruments, Inc.
英文描述： 32-BIT DYNAMIC RAM MODULE
中文描述： 32位動態(tài)RAM模塊
文件頁數(shù)： 6/9頁
文件大小： 140K
代理商： 2097152
TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAMMODULE
TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAMMODULE
SMMS649A – DECEMBER 1994 – REVISED JUNE 1995
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
’124BBK32F-60
’248CBK32F-60
’124BBK32F-70
’248CBK32F-70
’124BBK32F-80
’248CBK32F-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tAA
tCAC
tRAC
tCPA
tCLZ
tOH
tOFF
NOTE 6: tOFF is specified when the output is no longer driven.
Access time from column address
30
35
40
ns
Access time from CAS low
15
18
20
ns
Access time from RAS low
60
70
80
ns
Access time from column precharge
35
40
45
ns
CAS to output in low-impedance state
0
0
0
ns
Output disable time from start of CAS high
3
3
3
ns
Output disable time after CAS high (see Note 6)
0
15
0
18
0
20
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’124BBK32F-60
’248CBK32F-60
’124BBK32F-70
’248CBK32F-70
’124BBK32F-80
’248CBK32F-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tRC
tRWC
tPC
tRASP
tRAS
tCAS
tCP
tRP
tWP
tASC
tASR
tDS
tRCS
tCWL
tRWL
tWCS
tWRP
tCAH
tRHCP
tDH
tRAH
tRCH
tRRH
NOTES:
Cycle time, random read or write (see Note 7)
110
130
150
ns
Cycle time, read-write
155
181
205
ns
Cycle time, page-mode read or write (see Notes 7 and 8)
40
45
50
ns
Pulse duration, page mode, RAS low
60
100 000
70
100 000
80
100 000
ns
Pulse duration, nonpage mode, RAS low
60
10 000
70
10 000
80
10 000
ns
Pulse duration, CAS low
15
10 000
18
10 000
20
10 000
ns
Pulse duration, CAS high
10
10
10
ns
Pulse duration, RAS high (precharge)
40
50
60
ns
Pulse duration, W low
10
10
10
ns
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
Setup time, data before CAS low
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
Setup time, W low before CAS high
15
18
20
ns
Setup time, W low before RAS high
15
18
20
ns
Setup time, W low before CAS low
0
0
0
ns
Setup time, W high before RAS low (CBR refresh only)
10
10
10
ns
Hold time, column address after CAS low
10
15
15
ns
Hold time, RAS high from CAS precharge
35
40
45
ns
Hold time, data after CAS low
10
15
15
ns
Hold time, row address after RAS low
10
10
10
ns
Hold time, W high after CAS high (see Note 9)
0
0
0
ns
Hold time, W high after RAS high (see Note 9)
0
0
0
ns
7. All cycles assume tT = 5 ns.
8. To assure tPC min, tASC should be
≥
tCP.
9. Either tRRH or tRCH must be satisfied for a read cycle.
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