參數(shù)資料
型號(hào): 21176
英文描述: Designing 100BASE-TX? 86.8KB (PDF) System with the QFEX Family ?
中文描述: 設(shè)計(jì)100BASE - TX的? 86.8KB(PDF格式)系統(tǒng)?與QFEX家庭
文件頁(yè)數(shù): 14/15頁(yè)
文件大?。?/td> 86K
代理商: 21176
14
Designing 100BASE-TX Systems with the QFEX Family
Figure 9.
Power Plane Partitioning (Note 2)
REFERENCES
High-Speed Board Design Techniques
application note PID 16356A.
, AMD technical
Board Layout Considerations for Am79865 and
Am79866
, AMD Technical Application Note,
PID 16864A.
FASTPULSE MediaCAT
Pulse Engineering, PO Box 12235, San Diego, CA,
92112. (619) 674-8100
, Pulse Engineering, P958-50.
Design And Layout Rules Eliminate Noise Coupling in
Communication Systems
, Suilinski, James A. EDN,
6/20/96, pp. 95-100.
B
R3
T3
R1
QFEXr
C
R2
A3
A0
T1
T0
RJ45
RJ45
RJ45
RJ45
Magnetics
Magnetics
Magnetics
MLT3
MLT3
MLT3
MLT3
Magnetics
T2
R0
A2
A1
D
Legend
:
Group
Subgroup
Description
A
100 BASE-X PECL Plane
A0
Port 0 PECL Plane
A1
Port 1 PECL Plane
A2
Port 2 PECL Plane
A3
Port 3 PECL Plane
B
TTL/CMOS Signals
C
Chassis Plane
D
PDX Plane
Group
Subgroup
Description
R
(Note 1)
R0
Port 0 Receive Plane
R1
Port 1 Receive Plane
R2
Port 2 Receive Plane
R3
Port 3 Receive Plane
T
(Note 1)
T0
Port 0 Transmit Plane
T1
Port 1 Transmit Plane
T2
Port 2 Transmit Plane
T3
Port 3 Transmit Plane
Note 1:
The Analog Receive and Trans-
mit planes shown here are sam-
ple recommendations by the
MLT-3 transceiver vendor. Con-
sult with the vendors regarding
optimum system layout guide-
lines.
Note 2:
Ground planes need not be par-
titioned like power planes. Refer
to the section “Plane Partition-
ing and EMI Considerations.”
21176B-9
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