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參數(shù)資料
| 型號： | 21176 |
| 英文描述： | Designing 100BASE-TX? 86.8KB (PDF) System with the QFEX Family ? |
| 中文描述： | 設(shè)計(jì)100BASE - TX的？ 86.8KB（PDF格式）系統(tǒng)？與QFEX家庭 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大小： | 86K |
| 代理商： | 21176 |
6
Designing 100BASE-TX Systems with the QFEX Family
Signals to each QFEXr device means that those re-
spective signals are mapped 1:1 on each device. So,
100RIC TXE[7:4] signals are mapped directly to the
QFEXr device 2 signals TX_EN[3:0], or in the system,
to logical signals TX_EN[7:4]. CRS signals map di-
rectly from QFEXr devices to the 100RIC. The QFEXr
ENRCV signals are not directly part of the MII stan-
dard interface in the 100BASE-X standard, but con-
nect directly to the 100RIC’s RXE signals. It is
possible to add buffers to increase the drive of each
pin, but it is not required.
As a final note, it is highly recommended to provide AC ter-
mination on most signal lines. If a signal fans out to multiple
devices, each trace should be terminated accordingly.
Driving Multiple PHY’s
Buffers may be needed to create large unmanaged re-
peaters using the QFEXr device. In a sample 12-port
design, three QFEXr devices can share common sig-
nals without significant drive degradation, but to pro-
vide additional drive capability, reasonably fast buffers
should be used.
PCS
The PCS lies below the MII interface. It is in charge of
the following functions in 100BASE-X:
— Encoding and decoding MII data nibbles to and
from 5-bit code groups. This is accomplished by
using the 4B/5B algorithms.
— Generating Carrier Sense and Collision Detec-
tion indications.
— Serialization and deserialization of code groups
for transmission and reception on the underlying
PMA layer.
— Mapping of Transmit, Receive, Carrier Sense
and Collision Detection between the MII and the
underlying PMA layer.
The QFEXr device implements the PCS layer per the
100BASE-X standard and also add a scrambler/de-
scrambler block to complete the PCS functions, as
shown in Figures 6 and 7.
On receipt of data, after it has passed through the PMA
layer (clock recovery, see below), the serial data is de-
serialized and passed on as a 5-bit entity to the de-
scrambler block. Scrambling and descrambling is
offered on the QFEXr device as a means of reducing
EMI peaks in the radiated signal (data) caused by re-
petitive patterns of 0’s and 1’s. Scrambling is done by
adding the output of a random number generator to the
data signal. The descrambler does the reverse process
for received data. The scrambler/descrambler function
can be set to minimize emissions as needed on the
QFEXr device.
Following the descrambler block, received data is
aligned and decoded. Encoding and decoding is per-
formed using the 4B/5B code-group algorithms.
Decoding 5-bit PCS code groups into 4-bit MII groups
effectively reduces the 125-Mbps physical channel rate
to a 100-Mbps physical layer interface. The reverse
happens for transmission. Here, JK and TR delimiter
pairs are added (for transmission) or removed (for re-
ceive) from the packet when the data packet is aligned.
Refer to the 100BASE-X standard or the QFEXr data
sheet for the code-group mapping tables.
Once the data is decoded and converted into 4-bit nib-
bles, it is passed on to the MII interface on RXD[3:0] to
the repeater. All other MII signals, such as RX_ER and
RX_DV, are set appropriately.
Figure 6.
QFEXr Receive Path
Figure 7 illustrates the transmission process through
the QFEXr device from the MII. Data is received on
TXD[3:0], encoded into 5-bit PCS code groups,
SDI
±
RX
±
Receive
State
Machine
PDX
RX_CLK
4B/5B Decoder
Deserializer
Code Align
5
5
RXD[3:0], RX_ER
(Symbol Mode)
RXD[3:0]
(MII Mode)
Descrambler
5
Clock Recovery
21176B-6
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