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| 型號(hào)： | 21176 |
| 英文描述： | Designing 100BASE-TX? 86.8KB (PDF) System with the QFEX Family ? |
| 中文描述： | 設(shè)計(jì)100BASE - TX的？ 86.8KB（PDF格式）系統(tǒng)？與QFEX家庭 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 86K |
| 代理商： | 21176 |
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Designing 100BASE-TX Systems with the QFEX Family
5
enable) signals are connected to RXE inputs on the
repeater. RX_DV, RX_CLK and RX_ER all connect di-
rectly to the repeater.
Note:
implementing four independent MII ports, and clock
synchronization may be required to drive the four
RX_CLK signals to ensure minimal clock skew.
Finally, CRS and COL lines connect directly to the
repeater, as well as the management lines (MDC and
MDIO). Buffering is also recommended for driving mul-
tiple management lines if using the four independent
MII port mode.
Buffering may be needed for bussed signals if
Application Example: Interfacing to NSC 100RIC
To demonstrate the benefits of the shared MII interface,
the following text explains how to design a repeater
using the QFEXr device. The repeater used is National
Semiconductor’s 100RIC (DP83850), a 12-port re-
peater.
This sample design requires three QFEXr devices to
be connected to the 100RIC’s MII port. Figure 5
shows the logical connection between the QFEXr de-
vices and the 100RIC.
Figure 5.
Sample Application: Multiple QFEXr Connections to NSC 100RIC
A 12-port repeater is a straightforward design using
three QFEXr devices and the 100RIC. There is no extra
logic required, except for optional buffers which can be
used to ensure drive capability in all circumstances. For
ease of display, the signals are separated into two
types: those signals to/from all QFEXr devices, and
those to/from each QFEXr device.
Common signals from the 100RIC to all QFEXr devices
are TXD[3:0], RXD[3:0], CLK, RX_CLK, RX_DV,
RX_ER and TX_ER. Thus, each QFEXr device re-
ceives that group of signals from the 100RIC. Some
100RIC outputs will drive multiple inputs, such as
TX_ER, which will connect to 12 QFEXr TX_ER sig-
nals. It is possible to drive these inputs without buffers.
Also, some 100RIC inputs will receive multiple QFEXr
outputs, such as RXD[3:0], RX_CLK and RX_DV in a
multiple QFEXr system. However, there is limited
cause for concern regarding fanout, since only one port
and, therefore, only one QFEXr device will be transmit-
ting to the 100RIC at any one time. In the event of a col-
lision (one port transmits while another receives
simultaneously), the PHY (QFEXr) will notify the
100RIC with a JAM sequence (repeated out to all
ports), but still only one QFEXr device will be using the
bus at any one time. In this example, the system clock
is used instead of TX_CLK. The 100RIC does not have
collision indication inputs and cannot support
COL[3:0]. Both LCK (100RIC) and the three CLK
(QFEXr) signals are driven by a buffered system clock.
CLK
TXD[3:0]
RXD[3:0]
RXC
RX_DV
RX_ER
TX_ER
TX_RDY
TXE[11:8]
TXE[7:4]
TXE[3:0]
CRS[11:8]
CRS[7:4]
CRS[3:0]
RXE[11:8]
RXE[7:4]
RXE[3:0]
CLK
TXD[3:0]
RXD[3:0]
RX_CLK
RX_DV
RX_ER
TX_ER[3:0]
TX_CLK
COL[3:0]
TX_EN[11:8] (QFEXr 3)
TX_EN[7:4] (QFEXr 2)
TX_EN[3:0] (QFEXr 1)
CRS[11:8] (QFEXr 3)
CRS[7:4] (QFEXr 2)
CRS[3:0] (QFEXr 1)
ENRCV[11:8] (QFEXr 3)
ENRCV[7:4] (QFEXr 2)
ENRCV[3:0] (QFEXr 1)
(From System Clock)
100RIC
signals
Signals to/from
all QFEXr IC's
Signals to/from
each QFEXr IC
N/C
N/C
N/C
21176B-5
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