參數(shù)資料
型號(hào): 21176
英文描述: Designing 100BASE-TX? 86.8KB (PDF) System with the QFEX Family ?
中文描述: 設(shè)計(jì)100BASE - TX的? 86.8KB(PDF格式)系統(tǒng)?與QFEX家庭
文件頁(yè)數(shù): 7/15頁(yè)
文件大?。?/td> 86K
代理商: 21176
Designing 100BASE-TX Systems with the QFEX Family
7
aligned, scrambled (if necessary), and serialized for
the PMA layer.
Loopback modes within the PCS block are available in
the QFEXr device as follows:
— From MII {TX_ER, TXD[3:0]} to {RX_ER,
RXD[3:0]
— From the 4B/5B encoder output to the 5B/4B de-
coder input (after code alignment)
— From the scrambler output to the descrambler
input
Figure 7.
QFEXr Transmit Path
PMA
The PMA layer lies below the PCS interface. It is in
charge of the following functions in 100BASE-X:
— Clock recovery from the NRZI data provided by
the PMD
— Mapping of transmit and receive code-bits be-
tween the PMA’s client and the PMD
— Optionally, generating indication of carrier activ-
ity and carrier errors from the PMD
— Optionally, sensing receive channel failures, and
detecting and transmitting the Far End Fault
Indication (FEFI)
The QFEXr device uses an all digital CMOS core for
clock recovery called the Physical Data Transceiver
(PDX).
In transmit, after passing through the PCS, the 5-bit
symbol is clocked into the PDX, serialized, converted
to NRZI format, and shifted to the TX
PECL-compatible signal levels. The PDX uses system
CLK as the frequency and phase reference to gener-
ate the serial link data rate. Thus, the PDX requires a
continuous external reference that it can derive its in-
ternal clock from, which is multiplied by 5 to generate
the 125 Mbps channel rate. The external reference
clock must meet 100BASE-X frequency and stability
requirements (
±
50 ppm).
±
outputs at
When receiving, data coming into the RX
streamed into the PDX, which recovers the clock and
then uses the clock to recover the data. The data, in an
unframed 5-bit symbol, is then sent up to the PCS level
for further operations. The PDX is capable of recover-
ing data correctly within
±
clock signal.
±
inputs is
1000 ppm of the 25 MHz
Carrier Detect, Link Monitor, and Far End Fault Detect
and Generate functions are also provided by the
QFEXr device. Refer to the 100BASE-X standard for
details on these functions.
Loopback modes within the PMA block are available in
the QFEXr device as follows:
— From the 5-bit data output to the 5-bit data input
inside the PDX block
— From the PDX serial output to the PDX serial
input
Carrier Integrity Monitor
To protect the repeater from spurious fault conditions
as well as preserve communications, the 100BASE-X
standard has included features that should be imple-
mented in the various PHY layers, including FEFI, link
monitor, and CIM. Fault conditions can be caused by
faulty wiring and disconnected/connected wires.
The CIM is specified as a feature the repeater provides
(Clause 27). The CIM detects certain faults like the
False Carrier and informs the repeater. A False Carrier
is an indication of activity on the line, but is not a valid
packet of data (any carrier event that does not begin
with a valid start of stream delimiter). The repeater will
issue a Jam sequence (a series of 3s and 4s in hexa-
decimal) to all ports (except the receiver) and to the MII
to inform the ports of the false carrier and that nothing
should be received until the false carrier ends, or the
false carrier timer times out. If a successive false car-
rier signal follows, the receiving port is partitioned.
The CIM is part of the PMA interface and is the respon-
sibility of the repeater PMA to count false carrier events
and implement the necessary requirements per the
100BASE-X repeater section of the standard.
Many 100-Mbps repeater devices available today lack
the CIM feature, and it has fallen on the part of the PHY
device vendors to provide an interim solution. The
QFEXr device offers a full CIM feature for repeaters
21176A-7
TX
±
TX+/–
Transmit
State
Machine
PDX
TX_CLK
TXD[3:0], TX_ER
(MII Mode)
TXD[3:0]
(Symbol Mode)
TX_EN
5
4B/5B Encoder
/J/K/ Insertion
Serializer
Scrambler
5
TX_CLK
CLK
21176B-7
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