參數(shù)資料
型號(hào)： 21326
英文描述： Implementation of Write Allocate Application Note
中文描述： 在寫(xiě)分配應(yīng)用執(zhí)行情況的說(shuō)明
文件頁(yè)數(shù)： 14/22頁(yè)
文件大?。?/td> 241K
代理商： 21326
6
Programming Details
Implementation of Write Allocate in the K86 Processors
21326F/0—February 1999
Step 2: AMD-K6
-2 Processor Model 8/[F:8] and AMD-K6-
III
Processor
Model 9
The AMD-K6-2 processor and the AMD-K6-III processor use two
mechanisms (programmable within the WHCR) to determine
when to perform write allocates. A write allocate is performed
when either of these mechanisms detects that a pending write
is to a cacheable area of memory.
Before programming the WHCR or changing memory
cacheability/writeability, the BIOS must writeback and
invalidate the internal cache by using the WBINVD instruction.
In addition, the WHCR should enable the write allocate
mechanisms only after performing any memory sizing or typing
algorithms.
Write Handling
Control Register
(WHCR)
The WHCR contains two fields—the Write Allocate Enable
Limit (WAELIM) field, and the Write Allocate Enable
15-to-16-Mbyte (WAE15M) bit (see Figure 2).
Note:
The WHCR register as defined in the Model 6, Model 7, and
Model 8/[7:0] has changed in the Model 8/[F:8] and Model 9.
Figure 2.
Write Handling Control Register (WHCR)—MSR C000_0082h (Model 8/[F:8] and Model 9)
Write Allocate Enable Limit.
The WAELIM field is 10 bits wide. This
field, multiplied by 4 Mbytes, defines an upper memory limit.
Any pending write cycle that misses the L1 cache and that
addresses memory below this limit causes the processor to
perform a write allocate (assuming the address is not within a
range where write allocates are disallowed). Write allocate is
disabled for memory accesses at and above this limit unless the
processor determines a pending write cycle is cacheable by
15
22
0
63
Reserved
WAELIM
16
W
A
E
1
5
M
Note
:
Hardware RESET initializes this MSR to all zeros.
Symbol
WAELIM
WAE15M
Description
Write Allocate Enable Limit
Write Allocate Enable 15-to-16-Mbyte 16
Bits
31-22
17
21
31
32
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