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| 型號： | 21326 |
| 英文描述： | Implementation of Write Allocate Application Note |
| 中文描述： | 在寫分配應(yīng)用執(zhí)行情況的說明 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 241K |
| 代理商： | 21326 |
21326F/0—February 1999
Implementation of Write Allocate in the K86 Processors
What is Write Allocate
1
Application Note
Implementation of
Write Allocate in the
K86 Processors
What is Write Allocate
Write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the Level-1 (L1) data cache. The
behavior of the processor thereafter differs depending on
whether the processor model contains a Level-2 (L2) cache. The
AMD-K6
processor Model 6 and Model 7, and the AMD-K6-2
processor Model 8 do not contain a L2 cache, whereas the
AMD-K6-III processor Model 9 does contain a L2 cache.
Models 6, 7, and 8
After the L1 data cache miss, the processor performs a 32-byte
burst read cycle on the system bus to fetch the data-cache line
addressed by the pending write cycle. The data associated with
the pending write cycle is merged with the recently-allocated
cache line and stored in the processor’s L1 data cache. The final
MESI (Modified, Exclusive, Shared, Invalid) state of the cache
line depends on the state of the WB/WT# and PWT signals
during the burst read cycle and the subsequent cache write hit.
Model 9
After the L1 data cache miss, the processor checks for the cache
line in the L2 cache. If the line does not exist in the L2 cache,
the processor performs a 32-byte burst read cycle on the system
bus to fetch the data-cache line addressed by the pending write
cycle. If the line does exist in the L2 cache, the data is supplied
directly from the L2 cache, in which case a system bus cycle is
TM
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