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參數(shù)資料
| 型號： | 21326 |
| 英文描述： | Implementation of Write Allocate Application Note |
| 中文描述： | 在寫分配應(yīng)用執(zhí)行情況的說明 |
| 文件頁數(shù)： | 21/22頁 |
| 文件大?。?/td> | 241K |
| 代理商： | 21326 |
Programming Details
13
21326F/0—February 1999
Implementation of Write Allocate in the K86 Processors
feature and its registers without end-user intervention. This
automatic setup is recommended.
Figure 5.
Hardware Configuration Register (HWCR)—MSR 83h
AMD-K5 Processor Programming Example for Write Allocate Registers
The following cases show examples of programming the write
allocate feature for two types of systems:
Case 1
For systems without a memory hole and 16 Mbytes of total
memory:
Program the WATMCR MSR (ECX=85h) with top of memory
(0100h) and enable bits (0005h) to protect the fixed range
and above the top of memory
Use the WRMSR instruction and the 64-bit hex value
0000_0000_0005_0100h
Note:
For 8-Mbyte systems, program 0080h in the lowest 16 bits.
For 32-Mbyte systems, program 0200h in the lowest 16 bits.
I
Code Sample
;disable WA bit (bit 4 of HWCR)
MOV
ECX,83H
RDMSR
AND
EAX,NOT 10H
WRMSR
;program top-of-memory and control bits
MOV
ECX,85H
MOV
EAX,50100H
XOR
EDX,EDX
WRMSR
;read HWCR (83h)
;select WATMCR
;TME=1,PRE=0,FRE=1,TOM=0100h
8
7
6
5
4
3
2
1
0
31
D
I
C
D
D
C
D
B
P
D
C
D
S
P
C
Reserved
W
A
Symbol
DDC
DIC
DBP
WA
DC
Description
Disable Data Cache
Disable Instruction Cache
Disable Branch Prediction
Write Allocate Enable
Debug Control
000 Off
001 Enable branch trace usages
Bits
7
6
5
4
3–1
DSPC
Disable Stopping Processor Clocks 0
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