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參數(shù)資料
| 型號： | 21531G |
| 英文描述： | Programmable 8 bit Silicon Delay Line |
| 中文描述： | AMD的快閃記憶體快速參考指南- 2003年2月版 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 21531G |
12
Ordering Part Number Designators
Am29LV
640
D
U
90R
WH
I
OPTIONAL PROCESSING
Blank
=
Standard Processing
N
=
ESN devices
TEMPERATURE RANGE
C
=
I
=
Commercial (0
°
C to +70
°
C)
Industrial (–40
°
C to +85
°
C)
E
=
Extended (–55
°
C to +125
°
C)
PACKAGE TYPE
J
=
K
=
P
=
S
=
SK
=
Z
=
Thin Small Outline Packages (TSOP):
E
=
32, 40, or 48-Pin Standard Pinout (TS 048)
(for Am29F016/017 devices only,
E = 48-pin, E4 = 40-pin)
E2
=
40/44-pin Type-II Standard Pinout (TS 044)
F
=
32, 40, or 48-pin Reverse Pinout (TSR048)
(for Am29F016/017 devices only,
F = 48-pin, F4 = 40-pin)
F2
=
40/44-pin Type-II Reverse Pinout (TSR044)
Fine-Pitch Ball Grid Array Packages,
0.8 mm ball pitch (unless otherwise noted):
MA =
63-ball, 11 x 12 mm body (FSA063)
MD =
63-ball, 10.95 x 11.95 body (FSD063)
VA
=
44-ball, 9.2 x 8 mm body, 0.5 mm pitch (VDA044)
VK
=
80-ball, 11.5 x 9 mm body (VBB080)
VM =
64-ball, 8 x 9 mm (VBD064)
Rectangular Plastic Leaded Chip Carrier (PLCC)
80-pin Plastic Quad Flat Package (PQFP) (PQR080)
Plastic Dual Inline Package (PDIP)
44-pin Small Outline (SO) Package (SO 044)
44-pin Reverse Pinout Small Outline Package (SOR044)
56-pin Shrink Small Outline Package (SSOP) (SSO056)
Fine-Pitch Ball Grid Array Packages (continued)
WA =
48-Ball, 6 x 8 mm body (FBA048)
WB =
48-Ball, 6 x 9 mm body (FBB048)
WC =
48-Ball, 8 x 9 mm body (FBC048)
WD =
63-Ball, 8 x 14 mm body (FBD063)
WG =
40-Ball, 8 x 15 mm body (FBE040)
WH =
63-Ball, 12 x 11 mm body (FBE063)
WK =
47-Ball, 7 x 10 mm body, 0.5 mm ball pitch (FDD047)
WL =
48-Ball, 11 x 10 mm body, 0.5 mm ball pitch (FDE048)
WM =
48-Ball, 6 x 12 mm body (FBD048)
WP =
84-Ball, 11 x 12 mm body (FBF084)
WS =
80-Ball, 11 x 12 mm body (FBE080)
Fortified Ball Grid Array Packages,
1.0 mm ball pitch (unless otherwise noted):
PA
=
64-Ball, 13 x 11 mm body (LSA064)
PB =
80-Ball, 13 x 11 mm body (LAA080)
PC
=
64-Ball 13 x 11 mm body (LAA064)
PE =
80-Ball, 10 x 15 mm body (LAB080)
PG
=
64-Ball, 18 x 12 mm body (LAC064)
PH
=
80-Ball, 13 x 11 mm body (LSB080)
PI
=
80-Ball, 11 x 12 mm body (LSC080)
SPEED OPTION (t
ACC
), VOLTAGE REGULATION
1.8 Volt Devices
**(*)
=
2 or 3 digits: (Am29SL, DS) Indicates speed in ns, V
= 1.8–2.2 V
**(*)
=
(Am29BDS) 2 or 3 characters indicate clock rate, asynchronous read access, handshaking type. See listing notes.
2.5 V Devices
**(*)
=
(Am29BDD) 3 digits indicate initial burst or asynchronous read access
3 Volt MirrorBit Devices
**(*)(R)
=
Two (or three) digits: 1 (or 2) represent speed in ns x 10. Last digit indicates V
IO
range. 0 = no V
IO
. 1: V
IO
= V
CC
.
3: V
IO
= 3 V. 5: V
IO
= 1.8 V. “R” indicates regulated voltage range
3 Volt non-MIrrorBit Devices
**(*)R
=
2 or 3 digits: Indicates speed in ns; device is full voltage range. “R” indicates regulated voltage range.
*(*)1(R)
=
(Am29LV64xD/G) First two digits indicate speed in ns x 10. “1” indicates V
< V
; “R” indicates regulated voltage range
**
=
(Am29PDL) FIrst digit represents speed in ns x 10. Last digit indicates V
IO
range. 3: V
IO
= 3 V. 8: V
IO
= 1.8 V.
5 Volt Devices
*(*)0
=
Speed option ends in “0”: Indicates speed in ns. V
CC
= 5.0 V ±10% (4.5–-5.5 V)
*5
=
Speed option ends in “5”: Check table and/or data sheet for actual speed and voltage range.
(Am29F400) If part number has a “0” after the temperature range, then V
CC
= 5.0 V ±10% (4.5–-5.5 V)
SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION
T
=
Top boot sector
B
=
Bottom boot sector
H
=
Uniform sector device, WP# protects
highest addressed sector
L
=
Uniform sector device, WP# protects
lowest addressed sector
Uniform sector device
(UltraNAND only) 100% usable blocks
U/blank
J40
=
=
PROCESS TECHNOLOGY
B
=
C
=
D
=
0.32 μm technology
0.32 μm thin-film technology
0.23 μm thin-film technology
G
M
N
=
=
=
0.17 μm thin-film technology
0.23 μm MirrorBit technology
0.13 μm MirrorBit technology
DENSITY, BUS WIDTH, AND SECTOR ORGANIZATION
***(*)
=
Density is as noted in table. Digits broadly give an indication of device density.
Bus width and organization vary by family.
FLASH MEMORY DEVICE FAMILY
Am29BDS
=
1.8 Volt-only, Simultaneous
Read/Write, Burst Mode
1.8 Volt-only, Simultaneous Read/Write
1.8 Volt-only, Simultaneous Read/Write,
Page Mode
1.8 Volt-only
2.5 Volt-only, Simultaneous
Read/Write, Burst Mode
3 Volt-only (including MirrorBit)
Am29DS
Am29PDS
=
=
Am29SL
Am29BDD
=
=
Am29LV
=
Am29DL
Am29BL
Am29PL
Am29PDL
=
=
=
=
3 Volt-only, Simultaneous Read/Write
3 Volt-only, Burst Mode
3 Volt-only, Page Mode
3 Volt-only, Simultaneous Read/Write,
Page Mode
3 Volt-only, UltraNAND
TM
5 Volt-only
Am30LV
Am29F
=
=
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