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參數(shù)資料
| 型號： | 21531G |
| 英文描述： | Programmable 8 bit Silicon Delay Line |
| 中文描述： | AMD的快閃記憶體快速參考指南- 2003年2月版 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 21531G |
5
1.8 Volt-only Flash Memory
A
2
Density
Ordering Part Number
1
Voltage Range
Byte/Word
Count x Bus
Width
Additional Features,
Sector Size/Count
5
Device Number
Sector
3
Access Times
(ns)
Package
(Pin/Ball
Count)
4
Temp.
Range
V
CC
V
IO
1.65–
1.95
S
32 Mbit
Am29BDS320G
T, B
D3, D4,
D8, D9 (13.5)
7
VM (64)
I
1.65–
1.95
4 M x 16
WP#, ACC, CFI. Separate address and data buses. Bank split 4 x
16Mb. Banks A–D (Kw): [(4)8,(15)32] [(16)32] [(16)32] [(15)32,(4)8]
C8, C9,
C3, C4 (20)
7
2.7–
3.15
64 Mbit
Am29BDS640G
T, B
D3, D4,
D8, D9 (13.5)
7
WS (80)
I
1.65–
1.95
1.65–
1.95
4 M x 16
WP#, ACC, CFI. Separate address and data buses. Bank split 4 x
16Mb. Banks A–D (Kw): [(4)8,(31)32] [(32)32] [(32)32] [(4)8,(31)32]
C8, C9,
C3, C4 (20)
7
2.7–
3.15
64 Mbit
Am29BDS643G
T
7G (20),
7M (13.5),
5K (11)
8
VA (44)
I
1.7–
1.9
1.7–
1.9
4 M x 16
WP#. Multiplexed address/data bus. Bank split 4 x 16Mb. Banks A–D
(Kw): [(8)4,(31)32] [(32)32] [(32)32] [(8)4,(31)32]
128 Mbit
Am29BDS128H
T, B
D3, D4,
D8, D9 (13.5)
7
WS (80)
I
1.65–
1.95
1.65–
1.95
4 M x 16
WP#, ACC, CFI, Advanced Sector Protection. Separate address and
data buses. Bank split 4 x 16Mb. Banks A–D (Kw): [(4)8,(31)32]
[(32)32] [(32)32] [(4)8,(31)32]
C8, C9,
C3, C4 (20)
7
2.7–
3.15
56-pin TSOP
48/63 ball
Fine-pitch BGA
64-ball
Fortified BGA
MirrorBit Package Migration
48-pin TSOP
32 Mb
16 Mb
x8/x16,
x16 only
x8 only
256 Mb
512 Mb
64 Mb
128 Mb
Am29LV160MT/B
Am29LV320MT/B
Am29LV320MH/L
1
3
2
Am29LV160MT/B
Am29LV320MT/B
Am29LV640MT/B
Am29LV640MH/L
Am29LV640MT/B
Am29LV017M
Am29LV116M (4)
Am29LV033MU
Am29LV065MU
Notes:
T/B = Top or bottom boot sector. H/L = Uniform sector with highest or lowest addressed sector WP# protection. U = Uniform sectors without WP# protection.
(1) 48- to 56-pin migration. (2) MirrorBit products in these packages will include 1 Gbit devices. (3) 48- to 63-ball migration. (4) Am29LV116M has boot sectors;
all other devices shown have uniform sectors. (5) 40- to 48-pin migration.
2
5
Am29LV017M
Am29LV033MU
Am29LV065MU
Am29LV128MH/L
Am29LV256MH/L
Am29LV512NH/L
Am29LV128MH/L
Am29LV256MH/L
Am29LV512NH/L
Am29LV160MT/B
Am29LV320MT/B
Am29LV640MT/B
Am29LV320MH/L
Am29LV640MH/L
40/48-pin TSOP
48/63-ball
Fine-pitch BGA
Notes:
1.
2.
3.
4.
5.
Contact AMD or an AMD representative for availability. See Ordering Part Number Designators table for additional package and product details. Products listed in italics are not yet introduced.
Sim R/W = Simultaneous Read/Write feature: Read from one bank while writing to any other bank.
Sector architecture: U = Uniform, T = Top boot, B = Bottom boot.
Pin/ball count provided in parenthesis is for information only, and is not included in the actual ordering part number.
Features:
WP# = Write protect input. ACC = Programming acceleration input. SecSi Sector = Secured Silicon (unique/random ID). CFI = Common Flash Interface.
Bank & Sector Size/Count:
Bank contents are given
in square brackets. Sector counts are given in parentheses. Kw = kilowords, KB = kilobytes, Mb = megabits.
BDS323D asynchronous access time is given first (11A = 110 ns, 40 MHz clock speed), followed by the burst mode access time in parentheses.
BDS320G/640G/128H clock rate/asynchronous access: D = 54 MHz/70 ns, C = 40 MHz/90 ns. Voltage/handshaking type: 3 = 3 V V
IO
, reduced wait state handshaking; 4 = 3 V V
IO
, standard handshaking;
8 = 1.8 V V
IO
, reduced wait state handshaking; 9 = 1.8 V V
IO
, standard handshaking.
BDS643G clock rate/handshaking enabled: K = 66 MHz/yes; M = 54 MHz/yes; G = 40 MHz/yes. Asynchronous access: 7 = 70 ns; 5 = 55 ns.
6.
7.
8.
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