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| 型號： | 21921 |
| 英文描述： | Low-Frequency, Spread-Spectrum EconOscillator |
| 中文描述： | 接口1 Am186CC通信控制器到AMD斯坦福線性加速器中心設(shè)備使用增強的小型工業(yè)應(yīng)用筆記？ 57.1KB（PDF格式） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 57K |
| 代理商： | 21921 |
2
Interfacing the Am186CC Controller to an AMD SLAC Device Using Enhanced SSI
MPI HARDWARE OVERVIEW
The MPI buses of the QSLAC device and the DSLAC
device are very similar. Both are serial, master/
slave-type interfaces. A system or linecard
microprocessor is the master, and the interface is
designed so that multiple slaves (i.e., SLAC devices)
can be attached to a single master’s MPI bus, as
shown in Figure 1.
Figure 1.
Multiple SLAC Devices
The MPI bus signals, like those through most digital
buses, are of three types:
n
Data
n
Clock/control
n
Address
The QSLAC data line (DIO) pin is a bidirectional,
three-state serial bus. Some DSLAC devices, like the
Am79C02 DSLAC device, has separate Data In (DIN)
and Data Out (DOUT) pins, which can be strapped
together to look like the QSLAC device’s single DIO
pin. The data on this line consists of 8-bit bytes
transmitted most significant bit first, regardless of
direction. The master initiates all transfers by sending
a command byte to the SLAC device. Each command
has a predetermined length (number of bytes) and
direction (read or write). For example, if the master
microprocessor sends out command number 25 (read
GX filter coefficients) to the DSLAC device, the DSLAC
device knows to transmit two bytes. Because the
command determines which device is transmitting,
master or slave, the software drivers must be correct to
prevent bus contention, which could damage the
devices. Also, in the case of a read, the SLAC device
will not accept a new command until the old one is
finished (i.e., until all bytes have been received or
transmitted). Software verification is critical.
The clock signal (DCLK) is an input to the SLAC
device. The clock can run continuously or can be active
only during data transfers. The maximum frequency of
DCLK for both QSLAC and DSLAC devices is
4.096 MHz. Data is clocked into the SLAC device on
the rising edge of DCLK, but data is sent out on the
falling edge of DCLK. This common technique makes it
easier to satisfy setup and hold-time requirements.
DCLK can be stopped indefinitely in either the High or
Low state if the chip select input is held High.
Each of the individual SLAC devices on the MPI bus is
addressed (i.e., selected) by pulling one of the chip
select inputs Low. The QSLAC device has a single chip
select (CS) for all four channels, while the DSLAC
device has a separate chip select for each channel
(CS1 and CS2). The rising edge of the chip select
marks or frames the end of each byte; therefore, the
chip select line must go High for at least the minimum
off period before the next byte is read or written. The
DSLAC device’s minimum off period is 5
μ
s, while the
QSLAC device’s minimum is 2.5
μ
s.
If the QSLAC device receives 16 clocks with CS
asserted (Low), then the device resets.
In addition to the data, clock, and address pins, the
QSLAC device has an interrupt pin as part of the
microprocessor interface. This pin can be very useful in
some systems, but is not discussed in this application
note. A brief description of this pin is available in the
Am79Q02/021/031 QSLAC Data Sheet,
order #18503.
SSI HARDWARE OVERVIEW
The Enhanced Synchronous Serial Interface (SSI) of
the Am186CC controller was designed to interface
directly with AMD SLAC devices and to provide a
low-pin-count interface with application-specific
integrated circuits (ASICs). With the right clocks, the
Am186CC controller can drive the MPI bus at its
maximum rate.
The SSI bus transmits three signals, each on a
separate pin:
n
SDATA
n
SCLK
n
SDEN
All the pins are shared (i.e., multiplexed) with one of the
Am186CC controller’s 48 PIOs. This allows the SSI
pins to be used as PIOs if their normal SSI function is
not needed. The pins are PIOs by default.
The SDATA signal—like DIO—is a bidirectional,
three-state serial bus. Unlike DIO, a weak pullup or
pulldown resistor keeps the last value on the bus for
systems that cannot tolerate three-state inputs. The
data on this signal consist of 8-bit bytes, normally
transmitted least significant bit first, but SSI can be
programmed for MSB-first operation. The master/slave
protocol is controlled entirely with software.
The clock signal (SCLK) is active only during byte
transfers. It is an output signal. The frequency is
derived by dividing the frequency of the internal clock
by 2, 4, 8, 16, 32, 64, 128, or 256 (programmed with the
Micro-
processor
SLAC
Device
SLAC
Device
SLAC
Device
MPI Bus
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