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| 型號： | 21921 |
| 英文描述： | Low-Frequency, Spread-Spectrum EconOscillator |
| 中文描述： | 接口1 Am186CC通信控制器到AMD斯坦福線性加速器中心設(shè)備使用增強的小型工業(yè)應(yīng)用筆記？ 57.1KB（PDF格式） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 57K |
| 代理商： | 21921 |
4
Interfacing the Am186CC Controller to an AMD SLAC Device Using Enhanced SSI
In the case of the data hold time in Table 1, there is no
specification given in the Am186CC controller data
sheet for how quickly SDATA can change after the
clock goes Low. It is assumed that in the worst case,
SDATA instantaneously changes as soon as SCLK
goes Low. This means that the hold time provided by
the Am186CC controller is the same as the minimum
SCLK High period, which is specified by the QSLAC
device as 97 ns.
The chip-select-setup and hold times are given for
SDEN rather than PIOs as discussed previously. Even
though SDEN is driven by the SSI, SDEN is still
controlled by software by writing a 1 or 0 to the DE bit
in the SSI Control (SSCON) register. Because SDEN is
controlled by software, the actual delay is much longer
than specified. The same holds true if PIOs are used to
drive the SLAC device’s chip selects.
Table 3 gives the usable options for each of the
available speed grades and the resultant data transfer
rate. To achieve the maximum DCLK rate of 4 MHz, the
Am186CC controller's internal frequency must be 8,
16, or 32 MHz (÷ 2, 4, or 8).
Note:
These frequencies are not the orderable speed grades, but are frequencies chosen that are a multiple of the fastest MPI
clock, which is 4 MHz.
Table 1. Microprocessor Output (Data Write)
Timing
Parameter
QSLAC
Device
Requires
(ns, min)
30
30
70
0
Am186CC
Controller
Provides
(ns, min)
72
97
219
122
Timing
Conflicts
Data Setup time
Data Hold time
CS Setup time
CS Hold time
None
None
None
None
Table 2. Microprocessor Input (Data Read)
Timing
Parameter
Am186CC
Controller
Requires
(ns, min)
10
3
QSLAC
Device
Provides
(ns, min)
47
97
Timing
Conflicts
Data Setup time
Data Hold time
None
None
Table 3. Am186CC Controller Frequencies
Clock
Divisor
÷
2
÷
4
÷
8
÷
16
÷
32
÷
64
÷
128
÷
256
Am186CC
Controller
-20 MHz
–
–
2.5 MHz
1.25 MHz
625 KHz
313 KHz
156 KHz
78 KHz
Am186CC
Controller
-32 MHz
–
–
4 MHz
2 MHz
1 MHz
500 KHz
250 KHz
125 KHz
Am186CC
Controller
-40 MHz
–
–
–
2.5 MHz
1.25 MHz
625 KHz
313 KHz
156 KHz
Am186CC
Controller
-48 MHz
–
–
–
3.0 MHz
1.5 MHz
750 KHz
375 KHz
187.5 KHz
Am186CC
Controller
-50 MHz
–
–
–
3.13 MHz
1.56 MHz
781 KHz
391 KHz
195 KHz
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