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參數(shù)資料
| 型號： | 21921 |
| 英文描述： | Low-Frequency, Spread-Spectrum EconOscillator |
| 中文描述： | 接口1 Am186CC通信控制器到AMD斯坦福線性加速器中心設(shè)備使用增強的小型工業(yè)應(yīng)用筆記？ 57.1KB（PDF格式） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 57K |
| 代理商： | 21921 |
Interfacing the Am186CC Controller to an AMD SLAC Device Using Enhanced SSI
3
SSCON register). In the case of a 40-MHz device, this
allows for speeds up to 20 MHz. As with the SLAC
device, data is clocked out on the falling edge and
clocked in on the rising edge.
The enable signal, SDEN, is an output signal. It is
normally active High, but it can be programmed to be
active Low to match CS of the MPI interface. While
there is only one enable pin, PIOs can be easily used
as chip selects to connect multiple SLAC devices to the
SSI port.
CONNECTING SSI TO MPI
The hardware connection is very easy. Figure 2 shows
the connections for the QSLAC device.
If interfacing the Am186CC controller with the DSLAC
device (which has two chip selects) or with multiple
SLAC devices, simply use PIOs in place of SDEN (see
Figure 3). There is nothing special about PIO9 and
PIO10; any uncommitted PIOs work. If the SLAC
device has separate DIN and DOUT pins rather than a
DIO pin, simply tie them together.
TIMING CONSIDERATIONS
The tables on page 4 compare the timing requirements
for the worst cases. Each worst case is determined by
looking at the most stringent requirement to see if the
other end of the interface can meet the requirement.
There is only one speed grade for the QSLAC device,
but there are multiple speed grades for the Am186CC
controller, so each case has been looked at with the
worst possibility in mind.
The timing of the DSLAC device is largely the same as
the timing of the QSLAC device. The only difference is
that the Chip Select Off time (parameters 9 and 16) is
longer—5
μ
s versus 2.5
μ
s—on the DSLAC device.
When verifying the timing, there are two cases to
consider: microprocessor write cycles and
microprocessor read cycles. Table 1 on page 4 looks at
the write cycle case, while Table 2 examines read
cycles. These numbers are easily verified, but as an
example, the next few paragraphs explain how Table 1
was derived. Verifying Table 2 is left as an exercise for
the reader.
During a write cycle, the QSLAC device's DIO pin is an
input, so it has setup and hold timing requirements as
illustrated in Table 1. These requirements can be
obtained directly from the QSLAC device’s data sheet
as parameters number 10 and 11 (Input data setup
time, t
IDS
, and Input data hold time, t
IDH
). Chip select is
also an input, with similar setup and hold times. The
QSLAC device specifies these parameters separately
for the input (write) and output (read) cases so the
correct parameters are 6 and 7 (Chip select setup time,
input state t
ICSS
, and Chip select hold time, input state
t
ICSH
).
Determining what the Am186CC controller provides—
the right half of Table 1—is a little more complicated.
Remember that SCLK and DCLK are tied together (i.e.,
they are the same clock.) Because data from the
Am186CC controller is output on the falling edge of
SCLK and latched into the QSLAC device on the rising
edge of DCLK, there is one-half clock cycle between
the two events. Assume the worst case duty cycle the
QSLAC device can tolerate, which is parameter 3
(Data Clock Low Pulse Width, t
DCL
) at 97 ns. This is a
conservative assumption because SCLK is always
very close to 50%. The Am186CC controller data sheet
guarantees that SDATA is valid no more than 20 ns
after SCLK goes Low in parameter t
SLDV
(SCLK Low to
Data Valid). Subtracting this delay from the length of
the clock pulse (97–20=77) leaves 77 ns for setup time
before the rising edge of DCLK.
All the other setup and hold times in Table 1 and
Table 2 are calculated in a similar fashion, and as the
tables show, there are generous margins even in the
worst case.
Am186CC
Controller
(PQFP)
Am79Q02
QSLAC Device
(PLCC)
SDATA (pin 4)
→
→
DIO (pin 38)
SCLK (pin 3)
DCLK (pin 39)
SDEN (pin 2)
CS (pin 40)
Figure 2.
QSLAC Device Connections
Am186CC
Controller
(PQFP)
Am79C03
DSLAC Device
(PLCC)
SDATA (pin 4)
→
→
→
DIO (pin 21)
SCLK (pin 3)
DCLK (pin 19)
PIO10 (pin 2)
CS1 (pin 32)
PIO9 (pin 124)
CS2 (pin 31)
Figure 3.
DSLAC Device Connections
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