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| 型號： | 21921 |
| 英文描述： | Low-Frequency, Spread-Spectrum EconOscillator |
| 中文描述： | 接口1 Am186CC通信控制器到AMD斯坦福線性加速器中心設備使用增強的小型工業(yè)應用筆記？ 57.1KB（PDF格式） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 57K |
| 代理商： | 21921 |
Interfacing the Am186CC Controller to an AMD SLAC Device Using Enhanced SSI
5
SOFTWARE CONSIDERATIONS
The basics of using the SSI port from software can be
illustrated with two subroutines. The first subroutine
writes a byte to the SLAC device; the second reads a
single byte. These two routines, along with
initialization, form the core of the necessary drivers.
The SSI port appears as five registers in the Am186CC
controller’s peripheral control block. This 1-Kbyte block
can be located either in memory or in I/O space at the
location pointed to by the Peripheral Control Block
Relocation (RELOC) register. The RELOC register
resides in the last register address of the peripheral
control block, at offset 03FEh. Because the base
location of the block can be moved, the location of
individual registers is specified as an offset from the
RELOC register rather than as an absolute address.
The PIO ports and control registers are also located in
this block of addresses. At reset, the peripheral control
block is located at FC00h in I/O space. This places the
RELOC register at FFFEh.
Table 4 shows the five SSI registers. The bit-level
definitions of these registers are given in Table 5.
The Port Busy (PB) bit in the SSSTAT status register
goes High when a transmit or receive operation is in
progress. The DE bits control the state of SDEN and
enable transmission or reception. A write to the
SSTXD0 or SSTXD1 transmit register or a read of the
SSRXD receive register initiates the transfer. For a
complete functional description of these registers,
including the features not used here, refer to the
Am186CC Communications Controller Register Set
Manual
, order #21916.
Assuming the connections in Figure 2 on page 2, the
following steps are required to execute the Read
Revision Code Number Command (#30 = 73h) of the
QSLAC device.
Initialize the SSI registers:
1. Write the PIO Mode 0 register to enable the SSI
function on the multiplexed pins [PIOMODE0 bits
10, 11, 12 = 0]
2. Write the PIO Direction 0 register to enable the SSI
function on the multiplexed pins [PIODIR0 bits 10,
11, 12 = 0]
3. Write the SSI Mode/Status register to enable SSI
enhancements [SSSTAT bit 15 = 1]
4. Write SSI Control register to set MSB first, Low true
SDEN, and
÷
16 [SSCON = 0130h]
Send the command:
1. Enable transmit by setting DE High
[SSCON bit 0 = 1]
2. Write the command [SSTXD0 = 73h]
3. Wait for PB to go Low [SSSTAT bit 0 = 0]
4. Disable transmit by setting DE Low
[SSCON bit 0 = 0]
After waiting at least 2.5
μ
s, receive the data:
1. Enable receive by setting DE0 High
[SSCON bit 0 = 1]
2. Start reception (read SSRXD)
3. Wait for PB to go Low [SSSTAT bit 0 = 0]
4. Disable receive by setting DE0 Low
[SSCON bit 0 = 0]
5. Read revision number (read SSRXD)
Table 4. SSI Port Registers
Offset from PCB
Register
Mnemonic
SSSTAT
SSCON
SSTXD1
SSTXD0
SSRXD
Register Name
2F0h
2F2h
2F4h
2F6h
2F8h
SSI Mode/Status
SSI Control
SSI Transmit 1
SSI Transmit 0
SSI Receive
Table 5. Bit Level Definitions
Offset
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2F0h
SSSTAT ENHCTL
RE/TE DR/DT
PB
2F2h
SSCON
CLKP DENP
MSBF
CLKEXP
DE1
DE0
2F4h
SSTXD1
TXDATA
2F6h
SSTXD0
TXDATA
2F8h
SSRXD
RXDATA
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