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參數資料
| 型號： | 23380A |
| 英文描述： | SDRAM Performance Monitors with the ?lan?SC520 Microcontroller? 233KB (PDF) |
| 中文描述： | SDRAM的性能監(jiān)視器的？蘭？SC520微控制器？ 233KB（PDF格式） |
| 文件頁數： | 12/18頁 |
| 文件大?。?/td> | 233K |
| 代理商： | 23380A |
12
SDRAM Performance Monitors with the élanSC520 Microcontroller Application Note
PARAMETER VALUES AS PROBABILITIES
The performance parameters described above are
easy to represent by a single bit, for example, cache-hit
information. However, other parameters need more
than one bit, such as the number of cycles needed to
access external memory or the number of clock pulses
while the pipeline is stalled. These parameters must be
converted into a pulse stream consisting of several bits.
Measuring performance parameters is not a function of
the élanSC520 microcontroller. However, the example
shown in Figure 6 can be used to measure a perfor-
mance parameter that ranges between the value 0 and
4 and requires four bits.
Figure 6.
Performance Parameters
For example, if a parameter is measured to be three
cycles, then three bits of the 4-bit pulse stream must be
set. This pulse stream is serially clocked into the
ADDIE. There is no synchronous requirement for
presenting data to the ADDIE. New parameter data can
be sampled at any time and clocked into the ADDIE
convertor.
Different parameters have differing value ranges. The
example in Figure 6 has a value range of 0 to 4;
another parameter might have a value range 0 to 16. All
parameters are not required to be restricted to the
same data range. Adjusting the number of data bits
applied to each parameter’s data range efficiently
utilizes the ADDIE's restricted probability resolution.
An 8-bit ADDIE can be used to measure a parameter
with the value range of 0 to 4, then later used to
measure a parameter with the data range of 0 to 16. In
all cases, the ADDIE determines the probability of the
data stream being 1. For a value range of 0 to 4, a
probability value of 75% represents a measured value
of 3 (100% being 4).
For example, when generating a sample value 3, any
three bits can be set. The order is not important. How-
ever, dispersing the setting of the bits can have a small
advantage in reducing the variance in counter
operation.
RANDOM NUMBER GENERATION
The ADDIE operation requires a random number gen-
erator. A pseudo-random number generator is ideal for
this task. A maximum length (m-sequence) can be pro-
duced by feeding back selected stages of an n-stage
shift register. The required stages are modulo-2 com-
bined and used to produce the input signal for the first
stage. For an example of a random number generator,
refer to Figure 7 on page 13.
The ADDIE can be prompted to converge on the
required value by using random numbers that
correlate. This condition is achieved by selecting
consecutive stages of the shift register and inverting
the most significant bit (MSB). Hence, the MSB of the
current random number is inverted and becomes the bit
occurring just before the MSB of the next random
number.
The test data shown in Figure 7 on page 13 uses a
31-bit shift register with feedback taken from stages 3
and 31. The top eight or 12 bits were used to form the
required random number. A smaller (less than 31-bit)
shift register can also be used.
0
1
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
2
3
4
Parameter Values
Four Bits
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