參數(shù)資料
型號(hào)： 23380A
英文描述： SDRAM Performance Monitors with the ?lan?SC520 Microcontroller? 233KB (PDF)
中文描述： SDRAM的性能監(jiān)視器的？蘭？SC520微控制器？ 233KB（PDF格式）
文件頁(yè)數(shù)： 3/18頁(yè)
文件大?。?/td> 233K
代理商： 23380A
SDRAM Performance Monitors with the élanSC520 Microcontroller Application Note
3
Merging implies that the same byte location is not writ-
ten more than once. For example, four individual byte
transfers from address 0, 1, 2, and 3 are merged in the
write buffer to form a single DWORD, thus converting
four independent byte transfers into a single DWORD
transfer to SDRAM.
Collapsing is similar to merging with the exception that
the same byte locations can be written more than once.
For example, an Am5
x
86 CPU cache snoop, that is a
result of a PCI host bridge burst of four DWORD
transfer to SDRAM, first requires a cache line write-
back (as a result of a hit in the Am5
x
86 CPU’s write-
back cache). First, the cache line write-back data is
written to the write buffer, followed by the PCI host
bridge transfer to the same four DWORD addresses.
Because the write buffer supports collapsing, the
cache line that was written to the write buffer by the
CPU due to a write-back is over-written with the write
data from the PCI host bridge transfer, thus collapsing
on the cache’s write-back data. Instead of eight
DWORD transfers to SDRAM, the collapse feature of
the write buffer only requires four DWORD transfers to
SDRAM. The write buffer is intended to de-couple the
master’s write traffic from incurring the overhead
associated with SDRAM refresh cycles and page/bank
misses.
In addition to possibly reducing the total number of
write transactions to SDRAM, the merge/collapse
feature helps to assemble independent partial DWORD
transfers into complete DWORDs, so the overhead
associated with error correcting code (ECC) read-
modify-write cycles can be reduced. Read-modify-write
transfers are required for ECC support when a partial
DWORD write occurs to SDRAM. Complete DWORD
writes do not require a read-modify-write function.
To provide the merge and collapse features, the write
buffer incorporates a content-addressable memory
(CAM). The CAM performs a look-up of DWORD
addresses that currently exist within the write buffer
with an address presented by the Am5
x
86 CPU, PCI
host bridge, or GP bus DMA that requests the write
transfer. During a CPU or PCI host bridge burst
transfer,
each
DWORD address during the transfer is
searched within the CAM.
Either of the two performance monitor resources can
be configured to provide a hit average of the number of
write buffer hits that occurred during either an Am5
x
86
CPU, PCI host bridge, or GP bus DMA write transfer. A
hit implies that a merge or collapse of write data
occurred. Each DWORD write transfer to the write
buffer, either complete or partial, is monitored
independently of each transfer being a single DWORD
or a burst of two, three, or four DWORDs. A ratio of
write buffer HIT/MISS is provided by the performance
monitors.
Write Buffer Hit Monitoring Analysis
The write buffer provides a write data merge and col-
lapse feature where a write of data to a DWORD that
currently exists in the write buffer can be merged or col-
lapsed into the same location in the buffer. This feature
is used to reduce the overall number of consecutive
write transactions to the same location in SDRAM. This
feature also attempts to merge partial DWORD write
transfers into complete DWORDs in the effort to reduce
the number of ECC read-modify-write cycles to
SDRAM.
Either performance monitor can be used to provide a
write buffer hit average. This information can be used
to specify an optimal watermark setting for the write
buffer. A higher watermark setting allows more write
data to accumulate in the write buffer before write-
backs are initiated to SDRAM. This provides a greater
chance for data merging and collapsing to take place
and lessens the occurrences of writes from the write
buffer interrupting the read accesses. A lower
watermark setting causes the write buffer to request
SDRAM accesses with fewer DWORDs in the buffer.
This causes the write buffer to possibly interfere with
read accesses, but lessens the occurrence of
overflowing the write buffer during complete DWORD
transfers when write data merging and collapsing is
less likely to occur.
A lower hit average with a high watermark setting might
imply that most write data is a complete DWORD, thus
merging and collapsing is not occurring as often. In this
condition, a lower watermark setting is recommended
to prevent write buffer full occurrence. A higher hit
average with a low watermark setting might imply that
a high occurrence of write data merging or collapsing
exists. In this condition, a higher watermark setting is
recommended to allow the write buffer to absorb the
write activity, without interrupting read accesses.
Write Buffer Read Merge Monitoring
As mentioned in “Write Buffer Hit Monitoring Analysis”,
the write buffer merges and collapses data. Because
the write buffer’s CAM makes the merge and collapse
features during write transfers possible and only a
single entry will exist for any given DWORD address
that currently exists in the write buffer, data read
merging from the write buffer is possible. This implies
that a read request by either the Am5
x
86 CPU, PCI
host bridge, or GP bus DMA to an address that
currently exists in the write buffer does not require the
write buffer to first be flushed to SDRAM to maintain
data coherency prior to the read request being
satisfied. Standard first-in first-out (FIFO) buffering
techniques without a CAM function require that the
buffer be flushed prior to every read because the data,
in the buffer that pertains to the data being requested
during the read, is not known. Instead of the possible
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