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| 型號： | 23380A |
| 英文描述： | SDRAM Performance Monitors with the ?lan?SC520 Microcontroller? 233KB (PDF) |
| 中文描述： | SDRAM的性能監(jiān)視器的？蘭？SC520微控制器？ 233KB（PDF格式） |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 233K |
| 代理商： | 23380A |
2
SDRAM Performance Monitors with the élanSC520 Microcontroller Application Note
Block Diagram
The ADDIE performance monitors are integrated into
the SDRAM controller’s subsystem as shown in
Figure 1. The performance steering logic allows the
appropriate signals to be routed from the various com-
ponents of the SDRAM controller’s sub-system based
on the user’s configuration. Each ADDIE is capable of
functioning independently.
The performance monitor is implemented with two
ADDIE devices with multiplexor circuitry. The two
ADDIE devices select the parameter to be monitored
with a configuration register.
Figure 1.
Block Diagram of SDRAM Subsystem with ADDIE Performance Monitors
ADDIE PERFORMANCE MONITORING PARAMETERS
The performance monitors are capable of indepen-
dently monitoring the following parameters:
I
Write buffer hits (implying merge or collapse)
I
Read merge hits (from the write buffer)
I
Write buffer full occurrence
I
Read buffer hits
I
SDRAM page and bank misses
Each parameter is explained below in detail.
Write Buffer Hit Monitoring
The élanSC520 microcontroller’s SDRAM controller
contains a 32-rank write buffer with each rank providing
four bytes of write data storage. Combined, these ranks
provide up to eight cache lines of write data storage for
transfers initiated by either the Am5
x
86 CPU, PCI
host bridge (on behalf of a PCI master for writing data
to SDRAM), or GP bus DMA. A write transfer initiated
by either the Am5
x
86 CPU or host bridge master can
be a single 32-bit DWORD or a burst of up to four
DWORDs during a single tenure. Each DWORD write
transaction can be either four bytes or less. A DWORD
write transfer of three bytes or less is referred to as a
partial DWORD. The Am5
x
86 CPU does not burst par-
tial DWORDs and only bursts write data during a cache
copy-back or write-back. However, the PCI host bridge
can burst transfer with all complete DWORDs, all par-
tial DWORDs, or a combination of both. GP bus DMA
write transfers are never larger than two bytes.
The élanSC520 microcontroller’s write buffer supports
standard FIFO buffering and also supports a write data
merge and collapse feature. Write merging occurs
when a sequence of individual writes are merged into
a single DWORD.
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