參數(shù)資料
型號: 24FC65
廠商: Microchip Technology Inc.
英文描述: 64K 5.0V 1MHz CMOS Smart Serial EEPROMs(4.5~5.5V,64K位,10M次擦寫周期,IIC智能串行EEPROM)
中文描述: 64K的5.0V的CMOS 1MHz的智能(4.5?5.5V的,64K的位,1000萬次擦寫周期,國際進口智能串行EEPROM的串行EEPROM)
文件頁數(shù): 10/16頁
文件大?。?/td> 237K
代理商: 24FC65
24FC65
DS21125C-page 10
1997 Microchip Technology Inc.
FIGURE 7-1:
CACHE WRITE TO THE ARRAY STARTING AT A PAGE BOUNDARY
FIGURE 7-2:
CACHE WRITE TO THE ARRAY STARTING AT A NON-PAGE BOUNDARY
1
Write command initiated at byte 0 of page 3 in the array;
First data byte is loaded into the cache byte 0.
2 64 bytes of data are loaded into cache.
cache page 0
cache
byte 0
cache
byte 1
cache
byte 7
cache page 1
bytes 8-15
cache page 2
bytes 16-23
cache page 7
bytes 56-63
4
Remaining pages in cache are written
to sequential pages in array.
page 0 page 1 page 2 byte 0 byte 1
page 0 page 1 page 2
byte 7 page 4
page 4
page 3
page 7
page 7
array row n
array row n + 1
3
Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.
5 Last page in cache written to page 2 in next row.
1
Write command initiated; 64 bytes of data
loaded into cache starting at byte 2 of page 0.
cache
byte 0
cache
byte 1
cache
byte 7
cache page 1
bytes 8-15
cache page 2
bytes 16-23
cache page 7
bytes 56-63
page 0 page 1 page 2 byte 0 byte 1
page 0 page 1 page 2
page 4
page 4
page 3
page 7
page 7
array row n+1
4
Write from cache into array initiated by STOP bit.
Page 0 of cache written to page 3 of array.
Write cycle is executed after every page is written.
6 Last 3 pages in cache written to next row in array.
cache
byte 2
2
Last 2 bytes ‘roll ever’
to beginning.
3
5
Remaining bytes in cache
are written sequentially to
array.
array row n
Last 2 bytes
loaded into
page 0 of cache.
byte 2 byte 3 byte 4
byte 7
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