參數(shù)資料
型號: 25AA1024
廠商: Microchip Technology Inc.
英文描述: 1 Mbit SPI Bus Serial EEPROM
中文描述: 1兆位SPI總線串行EEPROM
文件頁數(shù): 6/30頁
文件大?。?/td> 459K
代理商: 25AA1024
25AA1024/25LC1024
DS21836D-page 6
Preliminary
2007 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 25XX1024 is a 131,072 byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol.
The 25XX1024 contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX1024 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
BLOCK DIAGRAM
TABLE 2-1:
INSTRUCTION SET
SI
SO
SCK
CS
HOLD
WP
STATUS
Register
I/O Control
Logic
Memory
Control
Logic
X
Dec
HV Generator
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
V
CC
V
SS
Instruction Name
Instruction Format
Description
READ
WRITE
WREN
WRDI
RDSR
WRSR
PE
SE
CE
RDID
DPD
0000 0011
0000 0010
0000 0110
0000 0100
0000 0101
0000 0001
0100 0010
1101 1000
1100 0111
1010 1011
1011 1001
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read STATUS register
Write STATUS register
Page Erase – erase one page in memory array
Sector Erase – erase one sector in memory array
Chip Erase – erase all sectors in memory array
Release from Deep power-down and read electronic signature
Deep Power-Down mode
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