CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.8 Event/Error Counters
100046C
Conexant
3-45
Number of ATM cells sent from FIFO port 1.
Table 3-24. External Framer, 57-Octet Mode Event/Error Counters
Address
Counter Name
Function
0x40
LINE_ PHY_CNTR_1
Not used.
0x41
LINE_ PHY_CNTR_2
Not used.
0x42
LINE_ PHY_CNTR_3
Not used.
0x43
LINE_ PHY_CNTR_4
LOCD events if parallel interface is used.
0x44
LINE_ PHY_CNTR_5
Not used.
0x45
LINE_ PHY_CNTR_6
Counts PLCP frame errors if there is an error in either A1 or A2 octets. Event also
appears on LINE_STATUS, bit 9.
0x46
LINE_ PHY_CNTR_7
Counts PLCP OOF events. Event also appears on LINE_STATUS, bit 5.
0x47
LINE_ PHY_CNTR_8
Counts PLCP BIP errors. Event also appears on LINE_STATUS, bit 10.
0x48
LINE_ PHY_CNTR_9
Counts PLCP FEBE errors. Event also appears on LINE_STATUS, bit 11.
0x49
COR_HEC_ERR
Counts corrected HEC errors. Event also appears on EVENT_STATUS, bit 0.
0x4A
UNCOR_HEC_ERR
Counts uncorrected HEC errors. Event also appears on EVENT_STATUS, bit 1.
0x4B
PAY_CRC_ERR
Counts payload CRC-10 errors, used in AAL3/4. Event also appears on EVENT_STATUS,
bit 2.
0x4C
PAY_LEN_ERR
Counts payload length errors, used in AAL3/4. Event also appears on EVENT_STATUS,
bit 3.
0x4D
NON_ZERO_GFC
Counts ATM cells received with non-zero GFC fields. Event also appears on
EVENT_STATUS, bit 4.
0x4E
CELL_SENT_CNT0
Number of ATM cells sent from FIFO port 0.
0x4F
CELL_SENT_CNT1
0x50
CELL_SENT_CNT2
Number of ATM cells sent from FIFO port 2.
0x51
CELL_SENT_CNT3
Number of ATM cells sent from FIFO port 3.
0x52
CELL_RCV_CNT0
Number of ATM cells received on FIFO port 0.
0x53
CELL_RCV_CNT1
Number of ATM cells received on FIFO port 1.
0x54
CELL_RCV_CNT2
Number of ATM cells received on FIFO port 2.
0x55
CELL_RCV_CNT3
Number of ATM cells received on FIFO port 3.
0x56
IDLE_CELL_CNT
Counts ATM cells received that match the idle cell header screens. Event also appears
on EVENT_STATUS, bit 6.
0x57
NON_MATCH_CNT
Counts ATM cells received that do not match any header screens. Event also appears on
EVENT_STATUS, bit 5.