參數(shù)資料
型號(hào)： 28F640P3
廠商： Intel Corp.
英文描述： Intel StrataFlash Embedded Memory
中文描述： 英特爾StrataFlash嵌入式存儲(chǔ)器
文件頁(yè)數(shù)： 40/82頁(yè)
文件大?。?/td> 749K
代理商： 28F640P3
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
34
Preliminary
10.0
Power and Reset Considerations
10.1
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is
recommended to power-up V
CC
, V
CCQ
and S-V
CC
together. Conversely, V
CC
, V
CCQ
and S-V
CC
must power-down together.
It is also recommended to power-up V
PP
with or slightly after V
CC
. Conversely, V
PP
must power-
down with or slightly before V
CC
.
If V
CCQ
and/or V
PP
are not connected to the V
CC
supply, then V
CC
should attain V
CC
Min before
applying V
CCQ
and V
PP
. Device inputs should not be driven before supply voltage = V
CC
Min.
Power supply transitions should only occur when RST# is low.
10.2
Power Supply Decoupling
When the device is accessed, many internal conditions change. Circuits are enabled to charge
pumps and voltages are switched. All this internal activity produces transient signals. The
magnitude of these transient signals depends on the device and the system capacitive and inductive
loading. To minimize the effect of these transient signals, a 0.1 μF ceramic decoupling capacitor is
required across each V
CC
, V
CCQ
, V
PP,
S-V
CC
to system ground. Capacitors should also be placed
as close as possible to the package balls.
10.3
Flash Reset Characteristics
By holding the flash device in reset during power-up/down transitions, invalid bus conditions can
be masked. The flash device enters a reset mode when RST# is driven low. In reset mode, internal
flash circuitry is turned off and outputs are placed in a high-impedance state.
After return from reset, a certain amount of time is required before the flash device is capable of
performing normal operations. Upon return from reset, the flash device defaults to page mode.
If RST# is driven low during a program or erase operation, the operation will be aborted and the
memory contents at the aborted block or address are no longer valid. See
Figure 24,
“
Reset
Operations Waveforms
”
on page 52
for detailed information regarding reset timings.
相關(guān)PDF資料
PDF描述
28F320C3 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器)
28F800C3 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器)
28F160C3 3 Volt Advanced Boot Block Flash Memory(3 V 高級(jí)快速引導(dǎo)塊閃速存儲(chǔ)器)
28F320D18 1.8 Volt Intel Dual-Plane Flash Memory(1.8 V Intel 雙平面閃速存儲(chǔ)器)
28F320J5 5 Volt Intel StrataFlash Memory(5 V 32M位英特爾StrataFlash存儲(chǔ)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F640W30 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
28F650 制造商:Cinch Connectors 功能描述:1 Lug Terminal Strip
28F651 制造商:Cinch Connectors 功能描述:2 Lug Terminal Strip
28F652 制造商:Cinch Connectors 功能描述:3 Lug Terminal Strip
28F653 制造商:Cinch Connectors 功能描述:4 Lug Terminal Strip
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