參數(shù)資料
型號： 28F800B3
廠商： Intel Corp.
英文描述： SMART 3 ADVANCED BOOT BLOCK 4-, 8-, 16-, 32-MBIT FLASH MEMORY FAMILY
中文描述： 智能高級啟動3座4 - ，8 - ，16 - ，32 - Mbit閃存家庭
文件頁數(shù)： 10/48頁
文件大?。?/td> 304K
代理商： 28F800B3
SMART 3 ADVANCED BOOT BLOCK
E
10
PRELIMINARY
The pin descriptions table details the usage of each device pin.
Table 2. Smart 3 Advanced Boot Block Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
21
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a program or erase cycle.
28F008B3: A[0-19], 28F016B3: A[0-20], 28F032B3: A[0-21],
28F800B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20]
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, identifier and status register data. The
data pins float to tri-state when the chip is de-selected or the outputs are
disabled.
DQ
0
–DQ
7
INPUT/OUTPUT
DQ
8
–DQ
15
INPUT/OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched.
Outputs array and identifier data. The data pins float to tri-state when the
chip is de-selected.
Not included on x8 products.
CE#
INPUT
CHIP ENABLE:
Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data
buffers during a read operation. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the Command Register and memory
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN:
Uses two voltage levels (V
IL
, V
IH
) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode
, which drives the outputs to High-Z, resets the Write State
Machine, and minimizes current levels (I
CCD
).
When RP# is at logic high, the device is in standard operation
.
When RP# transitions from logic-low to logic-high, the device resets all
blocks to locked and defaults to the read array mode.
WP#
INPUT
WRITE PROTECT:
Provides a method for locking and unlocking the two
lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked
,
preventing program and erase operations to those blocks. If a program
or erase operation is attempted on a locked block, SR.1 and either SR.4
[program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked
and
can be programmed or erased.
See Section 3.3 for details on write protection.
相關(guān)PDF資料
PDF描述
28F016SA16-MBIT Evaluation Kit/Evaluation System for the MAX5954L/MAX5954A
28F016SV 16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY
28F016SA 16-Mbit(1 Mbit x 16, 2 Mbit x 8) FlashFile Memory(16-M位(1 M位 x 16, 2 M位 x 8) FlashFile存儲器)
28F016XD 16-Mbit Synchronous Flash Memory(16M位DRAM接口閃速存儲器)
28F016XS 16-Mbit Synchronous Flash Memory(16M位同步閃速存儲器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F800B5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SMART 5 BOOT BLOCK. FLASH MEMORY FAMILY 2. 4. 8 MBIT
28F800B5B70 制造商: 功能描述: 制造商:undefined 功能描述:
28F800BV-B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-MBIT (512K X 16. 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
28F800BV-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-MBIT (512K X 16. 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
28F800BV-T/B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Boot Flash
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