參數(shù)資料
型號(hào)： 29F400T-90TC
廠商： Electronic Theatre Controls, Inc.
英文描述： 4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY
中文描述： 4MEGABIT（為512k × 8 / 256K × 16）5VOLT扇區(qū)擦除的CMOS閃存
文件頁數(shù)： 13/38頁
文件大?。?/td> 240K
代理商： 29F400T-90TC
BRIGHT Preliminary BM29F400T/BM29F400B
Microelectronics
Inc.
A Winbond Company
Publication Release Date: May 1999
- 13 -
Revision A1
Resume command (30H). Note that any other commands during the time-out will
RESET
the device
to the Read mode. The address pins are "don't cares" when writing the Erase Suspend or Erase
Resume commands.
When the Erase Suspend command is written during a Sector Erase operation, the chip will take
between 1 uS and 230 uS to suspend the erase operation and go into Erase Suspended mode. During
this time, the system can monitor the Data Polling or Toggle Bit write operation status flags to
determine when the device has entered erase suspend mode (see Write Operation Status section.)
The system must use an address of an erasing sector to monitor Data Polling or Toggle Bit to
determine if the Sector Erase operation has been suspended.
In Erase Suspend mode, the system can read data from any sector that is not being erased. A read
from a sector being erased will result in write operation status data. After the system writes the Erase
Suspend command and waits until the Toggle Bit stops toggling, data reads from the device may then
be performed (see Write Operation Status section). Any further writes of the Erase Suspend
command at this time will be ignored.
To resume operation of Sector Erase, the Erase Resume command (30H) should be written. Any
further writes of the Erase Resume command at this point will be ignored. Another Erase Suspend
command can be written after the chip has resumed Sector Erase operation.
DQ7
Data
Polling
The BM29F400 device features Data Polling as a method to indicate to the host the status of the
Byte/Word Programming, Chip Erase, and Sector Erase operations. When the Byte/Word
Programming operation is in progress, an attempt to read the device will produce the compliment of
the data last written to DQ7. Upon completion of the Byte/Word Programming operation, an attempt
to read the device will produce the true data last written to DQ7. When the Chip Erase or Sector
Erase operation is in progress, an attempt to read the device will produce a logical "0" at the DQ7
output. Upon completion of the Chip Erase or Sector Erase operation, an attempt to read the device
will produce a logical "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure
3.
For Chip Erase, the Data Polling is valid after the rising edge of the sixth
WE
pulse in the six write
pulse sequence. For Sector Erase, the Data Polling is valid after the last rising edge of the sector
erase
WE
pulse. For both Chip Erase and Sector Erase, Data Polling must be performed at sector
address within any of the sectors being erased and not a protected sector. Otherwise, the Data
Polling status may not be valid. Once the Internal Algorithm operation is close to being completed,
the BM29F400 data pins (DQ7) may change asynchronously while the output enable (
OE
) is
asserted low. This means that the device is driving status information on DQ7 at one instant and valid
data at the next instant of time. Depending on when the system samples the DQ7 output, it may read
status or valid data. Even if the device has completed the Internal Algorithm operation and DQ7 has a
valid data, data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 will be read on the
successive read attempts.
The Data Polling feature is only active during the Byte/Word Programming operation, Chip Erase
operation, Sector Erase Operation, or Sector Erase time-out window (see Table 7).
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