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參數(shù)資料
| 型號(hào)： | 3342-07 |
| 廠商： | Peregrine Semiconductor |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | PROGRAMMING BOARD FOR PE3342 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | UltraCMOS™ |
| 類型： | 整數(shù) N/PLL |
| 頻率： | 2.7GHz |
| 適用于相關(guān)產(chǎn)品： | PE3342 |
| 已供物品： | 板，線纜，文檔，軟件 |
| 其它名稱： | 3342-7 3342-7-ND PE3342 PB |
Product Specification
PE3342
Page 7 of 17
Document No. 70-0091-04
│ www.psemi.com
2005-8 Peregrine Semiconductor Corp. All rights reserved.
Lock Detect Output
A lock detect signal is provided at pin LD, via the
pin CEXT (see Figure 1). CEXT is the logical “NAND”
of PD_
U and PD_D waveforms, driven through a
series 2k ohm resistor. When the loop is locked,
this output will be HIGH with narrow pulses LOW.
Connecting CEXT to an external shunt capacitor
provides integration of this signal.
The CEXT signal is sent to the LD pin through an
internal inverting comparator with an open drain
output. Thus LD is an “AND” function of PD_
U
and PD_
D.
Serial Data Port
The Serial Data Port allows control data to be
entered into the device. This data can be directed
into one of three registers: the Enhancement
register, the Primary register, and the EE register.
Table 7 defines the control line settings required
to select one of these destinations.
Input data presented on pin 5 (Data) is clocked
serially into the designated register on the rising
edge of Clock. Data is always loaded LSB (B0)
first into the receiving register. Figure 4 defines
the timing requirements for this process .
Table 8. Serial Interface
S_WR
E_WR
EELoad
Register Loaded
0
Primary Register
0
1
0
Enhancement Register
0
X
1
EE Register
Figure 4. Serial Interface Timing Diagram
t
DHLD
t
DSU
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
t
EC
t
CE
E_WR
EELoad
Data
Clock
S_WR
Obsolete
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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