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參數(shù)資料
| 型號： | 3342-07 |
| 廠商： | Peregrine Semiconductor |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | PROGRAMMING BOARD FOR PE3342 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | UltraCMOS™ |
| 類型： | 整數(shù) N/PLL |
| 頻率： | 2.7GHz |
| 適用于相關(guān)產(chǎn)品： | PE3342 |
| 已供物品： | 板，線纜，文檔，軟件 |
| 其它名稱： | 3342-7 3342-7-ND PE3342 PB |
Product Specification
PE3342
Page 11 of 17
Document No. 70-0091-04
│ www.psemi.com
2005-8 Peregrine Semiconductor Corp. All rights reserved.
Gross EEPROM Programming Timing Grid
Figure 7 shows a gross PE3342 EEPROM
programming timing grid although each individual
step has been described thoroughly in previous
sections. It starts with EE Register load, and then
together with other parameters a Vpp_ERASE
negative pulse is applied to Vpp pin to erase the
EEPROM contents and followed by a Vpp_WRITE
pulse for EEPROM write cycle. The separation
between the Vpp_ERASE and Vpp_WRITE pulse
has to be at least 100 ms if mechanical relays are
used to avoid both being on at the same time.
After EE programming, the contents of the
EEPROM cells can be verified by setting
Enhancement Register Bit 1. A procedure shown
in Figure 8 is applied twice. The first time is to
load the EE Register from EEPROM and the
second time is to shift out the EE Register
contents through Dout pin.
Figure 7. Gross PE3342 EEPROM Programming Timing Grid
Data
S_WR
Vpp_ERASE
Vpp_WRITE
0V
3V
0V
3V
0V
12.5V
0V
-8.5V
25 ms
EE Register
load
EE PROM
Erase
EE PROM
Write
0V
40 ms
E_WR
0V
3V
EELoad
3V
EESel
0V
3V
Clock
0V
3V
Dout
0V
3V
>=100 ms
Rough time scale
The final set
of Dout is
EEPROM
content
Note: ENH/ (Pin 20) is at low (0) for this process.
EE Register
shifted out
through Dout
EE
Pro
g
ra
m
in
g
EE
v
e
ri
fy
CHANNEL
CODE
ENH code set's
Dout mux to EE
EE Register
load from
EEPROM
Obsolete
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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