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參數(shù)資料
| 型號： | 3342-07 |
| 廠商： | Peregrine Semiconductor |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 0K |
| 描述： | PROGRAMMING BOARD FOR PE3342 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | UltraCMOS™ |
| 類型： | 整數(shù) N/PLL |
| 頻率： | 2.7GHz |
| 適用于相關(guān)產(chǎn)品： | PE3342 |
| 已供物品： | 板，線纜，文檔，軟件 |
| 其它名稱： | 3342-7 3342-7-ND PE3342 PB |
Product Specification
PE3342
Page 12 of 17
2005-8 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0091-04
│ UltraCMOS RFIC Solutions
Figure 8. Details of EE register contents loaded from EEPROM and then shifted out Serially through
Dout pin - The procedure is performed twice.
In Figure 8, the first step is to program
Enhancement Register to set Bit 1 high (“1”) to
access EE Register Output Bit Function.
Subsequent action, which includes 19 Clock
pulses, allows the existing EE Register contents to
be shifted out the Dout pin and the EEPROM
contents are loaded to the EE Register. Since the
initial data existing in the EE Register could be
anything, the data must be flushed out before
clocking the contents of the EEPROM register out.
After the same procedure is duplicated, the Dout
output is the EEPROM contents. Note that only
19 Clock pulses are enough for the 20-bit EE
Register because the first bit data is already
present at Dout pin. Also ENH/ (Pin 3 in TSSOP
or Pin 20 in QFN) is set to low (“0”) to access the
Enhancement mode.
Data
S_WR
0V
3V
0V
Enhancement
Register
Programming
0V
E_WR
0V
3V
EELoad
3V
EESel
0V
3V
Clock
0V
3V
Dout
(example)
3V
EE Register
load from
EEPROM
EE Register
shifted out
through Dout
Rough time scale
0 1 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1
20 us
Note: ENH/ (Pin 20) is at low (0) for this process.
Obsolete
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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