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參數(shù)資料
| 型號(hào)： | 3342-07 |
| 廠商： | Peregrine Semiconductor |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | PROGRAMMING BOARD FOR PE3342 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | UltraCMOS™ |
| 類型： | 整數(shù) N/PLL |
| 頻率： | 2.7GHz |
| 適用于相關(guān)產(chǎn)品： | PE3342 |
| 已供物品： | 板，線纜，文檔，軟件 |
| 其它名稱： | 3342-7 3342-7-ND PE3342 PB |
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Product Specification
PE3342
Page 10 of 17
2005-8 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0091-04
│ UltraCMOS RFIC Solutions
EEPROM Programming
Frequency control data that is present in the EE
Register can be written to the non-volatile
EEPROM. All 20 bits are written simultaneously
in a parallel operation. The EEPROM is
guaranteed for at least 100 erase/write cycles.
Erase Cycle
The EEPROM should be taken through an erase
cycle before writing data, since the write operation
performs a logical AND of the EEPROM’s current
contents with the data in the EE Register. Erasing
the EEPROM is accomplished by holding the
S_WR, EESel, and EELoad inputs HIGH, then
applying one ERASE programming voltage pulse
to the VPP input (see Table 13). The voltage
source for this operation must be capable of
supplying the EEPROM erase cycle current
(IPP_ERASE, Table 5). The timing diagram is
shown in Figure 5.
Write Cycle
Using the Serial Data Port, the EE Register is first
loaded with the desired data. The EEPROM is
then programmed with this data by taking the
S_WR input HIGH and EESel input LOW, then
applying one WRITE programming voltage pulse
to the VPP input. The voltage source for this
operation must be capable of supplying the
EEPROM write cycle current (IPP_WRITE, Table
5). The timing diagram of this operation is shown
in Figure 6. Programming is completed by taking
the EELoad input LOW.
Note that it is possible to erroneously overwrite
the EE Register with the EEPROM contents
before the write cycle begins by unneeded
manipulation of the EELoad bit (see Table 10 ).
Table 13. EEPROM Programming
Figure 5. EEPROM Erase Timing Diagram
S_WR
EESel
EELoad
VPP
Function
1
25ms @
8.5V
Erase cycle
1
0
1
25ms @ +12.5V
Write cycle
Figure 6. EEPROM Write Timing Diagram
t
EEPW
EELoad
S_WR
EESel
V
PP_ERASE
0V
t
EESU
t
EESU
-
8.5V
t
VPP
t
VPP
t
EEPW
S_WR
V
PP_WRITE
0V
EESel
t
EESU
t
EESU
12.5V
0V
3V
EELoad
t
VPP
t
VPP
Obsolete
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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