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參數(shù)資料
| 型號： | 405GPR |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Power PC 405GPr Embedded Processor |
| 中文描述： | 405GPr的Power PC嵌入式處理器 |
| 文件頁數(shù)： | 26/57頁 |
| 文件大小： | 614K |
| 代理商： | 405GPR |
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405GPr – Power PC 405GPr Embedded Processor
32
AMCC
Revision 2.04 – September 7, 2007
Data Sheet
SDRAM Interface
MemData0:31
Memory data bus.
Notes:
1. MemData0 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
I/O
3.3V LVTTL
MemAddr12:0
Memory address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr0 is the least significant bit (lsb).
O3.3V LVTTL
BA1:0
Bank Address supporting up to 4 internal banks.
O
3.3V LVTTL
RAS
Row Address Strobe.
O
3.3V LVTTL
CAS
Column Address Strobe.
O
3.3V LVTTL
DQM0:3
DQM for byte lane: 0 (MemData0:7),
1 (MemData8:15),
2 (MemData16:23), and
3 (MemData24:31)
O3.3V LVTTL
DQMCB
DQM for ECC check bits.
O
3.3V LVTTL
ECC0:7
ECC check bits 0:7.
I/O
3.3V LVTTL
BankSel0:3
Select up to four external SDRAM banks.
O
3.3V LVTTL
WE
Write Enable.
O
3.3V LVTTL
ClkEn0:1
SDRAM Clock Enable.
O
3.3V LVTTL
MemClkOut0:1
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a PLL
or zero-delay buffer.
O3.3V LVTTL
External Slave Peripheral Interface
PerData0:31
Peripheral data bus used by PPC405GPr when not in external
master mode, otherwise used by external master.
Note: PerData0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerAddr0:31
Peripheral address bus used by PPC405GPr when not in external
master mode, otherwise used by external master.
Note: PerAddr0 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerPar0:3
Peripheral byte parity signals.
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0:3
As outputs, these pins can act as byte-enables which are valid for an
entire cycle or as write-byte-enables which are valid for each byte on
each data transfer, allowing partial word transactions. As outputs,
pins are used by either the pripheral controller or the DMA controller
depending upon the type of transfer involved. Used as inputs when
an external bus master owns the external interface.
I/O
5V tolerant
3.3V LVTTL
1, 7
[PerWE]PCIINT
Peripheral write enable. Low when any of the four PerWBE0:3 write
byte enables are low.
or
PCI interrupt. Open-drain output (two states; 0 or open circuit)
O
5V tolerant
3.3V PCI
Signal Functional Description (Sheet 3 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal Name
Description
I/O
Type
Notes
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相關代理商/技術參數(shù) |
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