參數(shù)資料
型號(hào)： 405GPR
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 405GPr Embedded Processor
中文描述： 405GPr的Power PC嵌入式處理器
文件頁(yè)數(shù)： 31/57頁(yè)
文件大小： 614K
代理商： 405GPR
405GPr – Power PC 405GPr Embedded Processor
AMCC
37
Revision 2.04 – September 7, 2007
Data Sheet
[TrcClk]GPIO9
Trace interface clock. A toggling signal that is always half of the CPU
core frequency. To access this function, software must toggle a DCR
bit
or
General Purpose I/O.
Note: Initialization strapping must hold this pin low (0) during reset.
O[I/O]
5V tolerant
3.3V LVTTL
1, 6
Ground pins
GND
Ground
Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and
T11-T16 are also thermal balls.
OVDD pins
OVDD
Output driver voltage—3.3V.
VDD pins
VDD
Logic voltage—1.8V.
Other pins
Reserved
Reserved—Except for AF4, do not connect signals, voltage, or
ground to these pins. AF4 must be tied to OVDD or GND.
Signal Functional Description (Sheet 8 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal Name
Description
I/O
Type
Notes
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