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參數資料
| 型號： | 42S16400A |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 1梅格位× 16位× 4銀行（64兆位）同步動態(tài)RAM |
| 文件頁數： | 5/55頁 |
| 文件大?。?/td> | 472K |
| 代理商： | 42S16400A |
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IS42S16400A
ISSI
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
13
Rev.C
04/16/03
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-6
-7
- 1 0
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
M a x
U nits
tCK3
Clock Cycle Time
CAS Latency = 3
6
—
7
—
10
—
ns
tCK2
CAS Latency = 2
—
10
—
10
—
ns
tAC3
Access Time From CLK(4)
CAS Latency = 3
—
6
—
6
—
7
ns
tAC2
CAS Latency = 2
—
9
—
9
—
9
ns
tCHI
CLK HIGH Level Width
2
—
2.5
—
3.5
—
ns
tCL
CLK LOW Level Width
2
—
2.5
—
3.5
—
ns
tOH3
Output Data Hold Time
CAS Latency = 3
2.5
—
2.5
—
2.5
—
ns
tOH2
CAS Latency = 2
2.5
—
2.5
—
2.5
—
ns
tLZ
Output LOW Impedance Time
—
0
—
0
—
0
ns
tHZ3
Output HIGH Impedance Time(5)
CAS Latency = 3
—
6
—
6
—
7
ns
tHZ2
CAS Latency = 2
—
9
—
9
—
9
ns
tDS
Input Data Setup Time
1.5
—
1.5
—
2.0
—
ns
tDH
Input Data Hold Time
0.8
—
0.8
—
1
—
ns
tAS
Address Setup Time
1.5
—
1.5
—
2.0
—
ns
tAH
Address Hold Time
0.8
—
0.8
—
1
—
ns
tCKS
CKE Setup Time
1.5
—
1.5
—
2.0
—
ns
tCKH
CKE Hold Time
0.8
—
0.8
—
1
—
ns
tCKA
CKE to CLK Recovery Delay Time
1CLK+3
—
1CLK+3
—
1CLK+3
—ns
tCS
CommandSetupTime(
CS,RAS,CAS,WE,DQM)1.5
—
1.5
—
2.0
—
ns
tCH
CommandHoldTime(
CS,RAS,CAS,WE,DQM) 0.8
—
0.8
—
1
—
ns
tRC
Command Period (REF to REF / ACT to ACT)
60
—
63
—
70
—
ns
tRAS
Command Period (ACT to PRE)
35
50,000
37
50,000
44
50,000
ns
tRP
Command Period (PRE to ACT)
16
—
16
—
18
—
ns
tRCD
Active Command To Read / Write Command Delay Time
16
—
16
—
18
—
ns
tRRD
Command Period (ACT [0] to ACT[1])
14
—
14
—
15
—
ns
tDPL3
Input Data To Precharge
CAS Latency = 3
2CLK
—
2CLK
—
2CLK
—
ns
Command Delay time
tDPL2
CAS Latency = 2
2CLK
—
2CLK
—
2CLK
—
ns
tDAL3
Input Data To Active / Refresh
CAS Latency = 3
2CLK+tRP
—
2CLK+tRP
—
2CLK+tRP
—ns
Command Delay time (During Auto-Precharge)
tDAL2
CAS Latency = 2
2CLK+tRP
—
2CLK+tRP
—
2CLK+tRP
—ns
tT
Transition Time
1
10
1
10
1
10
ns
tREF
Refresh Cycle Time (4096)
—
64
—
64
—
64
ms
Notes:
1. When power is first applied, memory operation should be started 100 s after Vcc and VccQ reach their stipulated voltages. Also
note that the power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL
(max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)
when the output is in the high impedance state.
相關PDF資料 |
PDF描述 |
|---|---|
| 42S16800A | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 42S32200 | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 4300-000 | EMI/RFI FILTER Hermetically Sealed |
| 4300-000LF | |
| 4300-001 | EMI/RFI FILTER Hermetically Sealed |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 42S16400B-6TLTR | 制造商:Integrated Silicon Solution Inc 功能描述: |
| 42S16800A | 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 42S16800L | 制造商:NEC 制造商全稱:NEC 功能描述:3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE |
| 42S16800L-A60 | 制造商:NEC 制造商全稱:NEC 功能描述:3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE |
| 42S16800L-A70 | 制造商:NEC 制造商全稱:NEC 功能描述:3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE |
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