參數(shù)資料
型號(hào)： 4565B2
廠商： LSI CORP
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁(yè)數(shù)： 17/61頁(yè)
文件大?。?/td> 1691K
代理商： 4565B2
4565B Ultramapper Full Transport Retiming Device
Hardware Design Guide, Revision 2
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
December 17, 2003
24
Agere Systems Inc.
AG4, AE5, AD5,
AC5, AB8, AB5
DS3DATAOUTCLK[6:1]
I pd DS3/E3/STS-1 Data Output Clock. 44.736 MHz, 34.368 MHz, or
51.84 MHz clock input and is typically connected to a crystal oscillator or
clocking chip.
This clock is required for M13, E13, or STS1LT applications and is typi-
cally connected to an oscillator. This clock is not required for DS3/E3 to
SONET/SDH mapping applications. In this case, DS3XCLK/E3XCLK is
needed for DS3/E3 DJA. For STS-1 to SONET mapping applications,
the TMUX can be used to supply the STS-1 rate DATAOUT clock and
this clock is therefore not needed. For STS-1
PDH applications, a
51.84 MHz clock must be supplied at this pin.
AE8, AD6, AC8,
AB6, AD3, AD2
DS3RXCLKOUT[6:1]
O
DS3/E3/STS-1 Receive Clock Output. 44.736 MHz
DS3/34.368 MHz E3/51.84 MHz STS-1 clock out to external circuit.
Table 2-11. DS3/E3/STS-1 In
Pin
Symbol
Type
Name/Description
W5, W8, V5,
AD1, AB2, W3
DS3POSDATAIN[6:1]
I pd
DS3/E3/STS-1 Positive Data Input. Either contains the positive-rail of
the B3ZS/HDB3 encoded input data, or single-rail NRZ data.
AA5, Y5, AC2,
Y4, AC1, V1
DS3NEGDATAIN[6:1]
I pd
DS3/E3/STS-1 Negative Data Input. Either contains the negative-rail
of the B3ZS/HDB3 encoded input data or, in single-rail mode, this input
may be used to count bipolar violations.
AB4, AF1, AE1,
V3, V4, AB1
DS3DATAINCLK[6:1]
I pd
DS3/E3/STS-1 Data Input Clock. 44.736 MHz, 34.368 MHz, or
51.84 MHz clock for the DS3/E3/STS-1 positive and negative data
inputs.
Table 2-12. NSMI/STS-1 In
Pin
Symbol
Type
Name/Description
AN27, AP27,
AM24
NSMIRXDATA[3:1]
I pd
Network Serial Multiplex Interface (NSMI) Receive* Data. This is used in
the following applications:
I STS-1 rate clear-channel receive data to SPEMPR.
I DS3/E3 rate clear-channel receive data to M13/E13.
Additionally, it could be used as a SONET compliant STS-1 input signal to
STS1LT from external LIU.
* The transmit path is toward the high-speed fiber output, and the receive path is from the high-speed input. Low-speed inputs, e.g., NSMIRXDATA, on
the transmit path, are labeled receive. Low-speed outputs, e.g., NSMITXDATA, on the receive path, are labeled transmit.
AG21, AK28,
AJ22
NSMIRXCLK[3:1] I/O pd NSMI Receive Clock. Used in the following applications:
I Output (51.84 MHz) for the STS-1 rate clear-channel application.
I Output (44.736 MHz/34.368 MHz) for the DS3/E3 application.
Additionally, it could be used as an input clock for SONET compliant
STS-1 to STS1LT from external LIU.
AP29, AL23,
AL22
NSMIRXSYNC[3:1] I/O pd NSMI Receive Frame Sync. Used in the following applications:
I Output receive control frame sync signal for M13/E13.
I Output receive control frame sync signal for SPEMPR.
Additionally, it could be used to carry STS-1 input transmit clock for STS1LTs.
AL24, AK22,
AK21
RXDATAEN[3:1]
O
NSMI Receive Data Enable. This is used for an 8-pin NSMI mode receive
clock. More information will be published in a separate operational guide.
Table 2-10. DS3/E3/STS-1 Out
Pin
Symbol
Type
Name/Description
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