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參數(shù)資料
| 型號： | 4565B2 |
| 廠商： | LSI CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909 |
| 封裝： | PLASTIC, BGA-909 |
| 文件頁數(shù)： | 52/61頁 |
| 文件大?。?/td> | 1691K |
| 代理商： | 4565B2 |
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4565B Ultramapper Full Transport Retiming Device
Hardware Design Guide, Revision 2
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
December 17, 2003
56
Agere Systems Inc.
7.4 Asynchronous Read Mode
Notes:
ADDR [20:0]
Address is asynchronously passed from the host bus to the internal bus. The address will be available throughout the entire cycle.
CSN (Input)
Chip select is an active-low signal.
ADSN (Input) Address strobe is active-low.
DSN (Input)
Data strobe is active-low.
RWN (Input)
The read (H) write (L) signal is always high during a read cycle.
DTN (Output) Data transfer acknowledge (active-low). DTN is driven out of 3-state to inactive-high on the assertion of CSN. When the internal transac-
tion is complete, DTN goes active-low. DTN is then driven high again when either ADSN or DSN is deasserted. DTN will become 3-stated
when CSN is high.
DATA [15:0]
16-bit data bus.
Figure 7-4. Microprocessor Interface Asynchronous Read Cycle—MPMODE Pin = 0
Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications
Symbol
Parameter
Setup
(Min)
Hold
(Min)
Delay
(Min)
Delay
(Max)
Unit
tCSFDSF
CSN Fall Setup and Hold to DSN Fall
0
—
ns
tAICSR
CSN Rise to ADDR Invalid
—
0
—
ns
tAVADSF
ADDR Valid Setup and Hold to ADSN Fall
1.0
—
ns
tADSRAI
ADSN Rise to ADDR Invalid
—
1.42
—
ns
tAVDSF
ADDR Valid Setup and Hold to DSN Fall
0
—
ns
tDSNRAI
DSN Rise to ADDR Invalid
—
0
—
ns
tRWFDSF
RWN Fall Setup and Hold to DSN Fall
0
—
ns
tDSRRWR
DSN Rise to RWN Rise
—
0
——
ns
tDVDSF
DATA Valid Setup and Hold to DSN Fall
0
—
ns
tDSRDI
DSN Rise to DATA Invalid
—
0
—
ns
tCSFDTR
CSN Fall to DTN Rise
—
5.2
16.0
ns
tDSFDTF
DSN Fall to DTN Fall
—
0
—
*
ns
tADSRDTR ADSN or DSN Rise to DTN Rise
—
2.9
13.3
ns
tCSRDT3
CSN Rise to DTN 3-state
—
2.9
13
ns
* Certain registers in the VTMPR block have a very long acknowledge cycle (in the order of 32 MPCLK cycles). The reason for this is that those registers
can also be accessed by the VTMPR lower order path overhead interface as part of SONET overhead termination functions. Therfore, the user must
insert a long enough delay or use the DTN signal to read/write these registers correctly.
ADDR[20:0]
CSN
ADSN
DSN
DTN
DATA[15:0]
tADSRD3
tCSRDT3
tADSRDTR
tCSFDSF
RWN
tAVADSF
tAVDSF
tAICSR
tADSRAI
tDSNRAI
tDTVDV
tDSFDTF
tCSFDTR
HIGH Z
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